I have a register field called SOFTWARE_RESET. Normally after the user write it to 1, it will first be 1, then self clear to 0 after 1 cycle. (I think this is different from RAL’s W1C access, which mirrored value will immediately turn to 0 after you wrote 1 to it, and W1C won’t do bus access if you set it to 1 and the mirrored value is 0)
But if the internal clock is disable, i.e. A field called INT_CLK_DIS is 1
and there is no external clock supplied to the dut through a pin called EX_CLK,
then it shouldn’t reset the dut. The SOFTWARE_RESET field won’t do self clear too. Until the clock reappear.
These kind of temporal behaviour clearly can’t be implemented inside ral model solely because it needs to wait for a signal(the clock) to trigger the value change.
Should I implemented this model in uvm_reg_predictor which has run_phase()?