If virtual sequencer contain a source sequencer and and destination sequencer and in test I am calling seq.start(envh.v_seqrh) then how ill the tool know to start the sequences on source sequencer or destination sequencer

UVM
1

The virtual sequencer is extended from uvm_sequencer base class.
class router_virtual_sequencer extends uvm_sequencer #(uvm_sequence_item);

`uvm_component_utils(router_virtual_sequencer)
router_env_config env_cfg;

// Source sequencer handel
router_src_sequencer src_seqrh[];

// Destination sequencer handel
router_dst_sequencer dst_seqrh[];

function new(string name = "router_virtual_sequencer", uvm_component parent);
	super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
	if(!uvm_config_db#(router_env_config)::get(this,"","router_env_config",env_cfg))
		`uvm_fatal("V_SEQRH","Getting failed in virtual sequencer check it")
	dst_seqrh = new[env_cfg.no_of_dst_agent];
		src_seqrh = new[env_cfg.no_of_src_agent];
endfunction

endclass: router_virtual_sequencer

In my test extended class if I write in the below format what will happen…?

class router_test_extd extends router_test;

`uvm_component_utils(router_test_extd)

router_src_ext_seq src_seq;

function new(string name = "router_test_extd",uvm_component parent);
	super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
	super.build_phase(phase);
endfunction

task run_phase (uvm_phase phase);
	src_seq = router_src_ext_seq::type_id::create("src_seq");
	phase.raise_objection(this);
		for(int i =0; i<no_of_src_agent;i++)
			//**src_seq.start(envh.v_seqrh.src_seqrh[i]);**
                            **src_seq.start(envh.v_seqrh);
	phase.drop_objection(this);
endtask

endclass

2

The sequencers in your virtual sequencer should be assigned the handles of sequencers that are present in source and destination agents. And in virtual sequence you need specify which sequences you want to start on source and destination sequencers inside your virtual sequencer

3

Additionally for such usage of virtual sequencer, you need to create virtual sequences where we can declare parent sequencer using `uvm_declare_p_sequencer.
Basic skeleton for the virtual sequence is as below:

class vir_seq extends uvm_sequence;

  `uvm_object_utils(vir_seq)
  `uvm_declare_p_sequencer(router_virtual_sequencer)

  router_src_ext_seq src_seq;
  ...
  ...

  task body();
    src_seq = router_src_ext_seq::type_id::create("src_seq");
    for(...)
      src_seq.start(p_sequencer.src_seqrh[index]);
  endtask 

endclass : vir_seq

From test, you can start vir_seq using v_seqrh.