Hierarchical uvm_reg_block add hdl path

UVM
1

I have a reg block with multiple sub-block … something like this:

I am struggling to add the correct hdl path for all these.

HDL path for a, b c and like something like dut.i_xyz.a, dut._ixyz.b etc

class reg_blk extends uvm_reg_block;
   rand sub_reg_block_a a;
   rand sub_reg_block_b b;
   rand sub_reg_block_c c;

   function new(string name = "reg_blk");
			super.new(name);
   endfunction: new

   function void build();
	this.default_map = create_map("", 0, 4, UVM_LITTLE_ENDIAN, 0);
	this.a= sub_reg_block_a::type_id::create("a",,get_full_name());
	this.a.configure(this, "");
	this.a.build();
	this.default_map.add_submap(this.a.default_map, `UVM_REG_ADDR_WIDTH'hA90);
   endfunction

endclass

I have tried this:

reg_blk_inst.set_default_hdl_path("dut.i_xyz")
reg_blk_inst.a.add_hdl_path("a")