Verification Academy

Topic	Replies	Views	Activity
Suggestions for class definition for user_item UVM UVM , Suggestions-for-class-definition-for-user_item	0	281	November 15, 2022
Value initialization with task input SystemVerilog SystemVerilog , task-input-initialization	4	1204	November 15, 2022
Fork in a for loop SystemVerilog SystemVerilog , automatic , for-loop , fork	3	683	November 15, 2022
What is the need of this assignment? SystemVerilog SystemVerilog	4	579	November 14, 2022
Need help with the error SystemVerilog SystemVerilog , error , Verilog , python , base_test-uvm_tlm_fifo , help	1	737	November 14, 2022
4bits of decimal precision SystemVerilog SystemVerilog	2	430	November 13, 2022
Constraint solver : very slow for array randomization SystemVerilog SystemVerilog	2	544	November 12, 2022
Cookbook "Vertically Integrated Environment Example" UVM UVM , Cookbook-RegistersIntegrating	0	332	November 12, 2022
Disabling a driver within DUT SystemVerilog SystemVerilog , Disable-multiple-drivers-SystemVerilog-Verification	1	489	November 11, 2022
Why i'm i not able to import driver in cocotb SystemVerilog SystemVerilog , cocotb	0	495	November 11, 2022
Cross_Coverage_Related_Doubts SystemVerilog SystemVerilog , System-Verilog , SystemVerilog-FunctionalCoverage , cross-coverage-bins , cross-coverage-bins-constraints	3	721	November 11, 2022
Systemverilog DPI-C UVM UVM , Cookbook-CBasedStimulus	4	1525	November 11, 2022
Question related to add_submap UVM UVM , Question-related-to-add_submap	0	462	November 11, 2022
Ho to pass a dynamic array to a constant function SystemVerilog SystemVerilog , systemverilog-constant-function-syntheisis	2	791	November 11, 2022
Delay a signal by a certain period and also get the opposite polarity of the signal as output? SystemVerilog SystemVerilog , System-Verilog	3	1105	November 11, 2022
Adding additional ports to driver/sequencer pair UVM UVM , uvm_sequence , uvm_sequencer , uvm-uvm_driver- , UVM-DRIVER-INTERFACE	1	627	November 10, 2022
Interview_Question_Regarding_Assertion SystemVerilog SystemVerilog , SVA , implication-assertion , Assertions-clock	1	681	November 10, 2022
Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it? SystemVerilog SystemVerilog , Package , module , package-inside-module	6	907	November 10, 2022
Is it possible to sample a signal on the same edge on which it was driven in sv? SystemVerilog SystemVerilog , Clocking-Block , sampled-value	5	2073	November 9, 2022
Arrays SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	3	554	November 9, 2022
DUT signals are not taking proper values while writing Systemverilog testbench SystemVerilog SystemVerilog	2	335	November 8, 2022
How to implement soft constraint without soft keyword SystemVerilog SystemVerilog , constraint-randomization	1	474	November 8, 2022
Coverpoint bins with enum excluded Coverage SystemVerilog , Coverage , coverpoint , enum	1	924	November 8, 2022
Help - QuestaSim can't randomize for array of union SystemVerilog SystemVerilog , questasim , assertstdrandomizevariable , Union	2	618	November 8, 2022
Task with for loop - starts and finishes at the same simulation timestep SystemVerilog SystemVerilog	2	667	November 7, 2022
How to use * in string SystemVerilog SystemVerilog	1	360	November 7, 2022
Dynamic Address Mapping from Cookbook UVM UVM , Dynamic-Address-Mapping-from-Cookbook	2	505	November 7, 2022
How to print/display full backdoor access path of a register? UVM UVM , UVM-backdoor-access	5	1836	November 7, 2022
Why we are suggested to use $urandom rather than $random SystemVerilog SystemVerilog , urandom , random	4	2047	November 7, 2022
SVA - set the number of failures Announcements Announcements , limit-SVA	1	515	November 6, 2022