Disabling a driver within DUT

SystemVerilog
,
1

I have developed a testbench for my DUT in SV (not UVM based) where I drive stimulus to the inputs of DUT and monitor the outputs of DUT and this works fine. However, my DUT consists of several sub-blocks A, B and C so when I drive from the testbench I drive the ports of DUT which in turn drives A which is connected to B and B to C and I monitor the output of C which drives the primary outputs of DUT.

However, to improve simulation time I would in the same setup like to drive the inputs of B and monitor its output like B was the DUT. I would like to drive the inputs of B by driving the input ports of DUT.B and monitor the output ports of DUT.B. Is it possible to do this in an elegant manner without inserting muxes within DUT for the purpose of verification. In other words while testing B I would like A to drive Z to B so my testbench can drive the inputs of DUT.B without causing X’s on its inputs.

Thanks

Noel

2

In reply to noel:

You can use force statements to override the signals going into B.

I don’t see how this improves simulation performance versus simulating block B by itself. You would need to remove the stimulus to blocks A and C, and do it in such a way that it does not affect what you want to simulate and monitor in block B. For example you cannot force the clock inputs to A and C to prevent them toggling unless there are buffers separating that from the clock going into B.