Task with for loop - starts and finishes at the same simulation timestep

SystemVerilog
1

I have this task that just reads a bunch of memory addresses and writes the data to a file (this task appears to be working). I added some $display statments to see what time it starts at and what time it finishes at, and it appears to start and finish at the same simulation time. There is a for loop in here that loops through >4000 times. Shouldn’t this take some amount of time in the simulation? Not sure how this part works exactly. Here is the code for the loop:


begin
	if (i_yuv_format != 1'b1) begin
		for (int i = 0; i < (i_frame_width*i_frame_height); i=i+1) begin
			this.vps_if.task_read_mem((i_mem_addr + (8*i)), 8, read_mem);
			$fwrite(i_file_handler, "%u", read_mem);
		end
	end
	else begin
		$display("[%0t]: Starting dump_ddr_to_file task", $time); // added this for debugging
		
		for (int i = 0; i < ((i_frame_width*i_frame_height*2)/8); i=i+1) begin
			this.vps_if.task_read_mem((i_mem_addr + (8*i)), 8, read_mem);
			$fwrite(i_file_handler, "%u", read_mem);
		end

		$display("[%0t]: Finished dump_ddr_to_file task", $time); // added this for debugging
	end
end

Here is what I see on the console:

[385500 ns]: Starting dump_ddr_to_file task
[385500 ns]: Finished dump_ddr_to_file task

2

In reply to ianmurph:

Without knowing how much time task_read_mem is supposed to take, it is difficult to know what your problem is. It’ possible it’s doing a “backdoor” read which would take 0 time.

You can also use $realtime instead of $time in case there are fractional ns involved. You also need to check the time precision of the module where this code exists.

3

In reply to dave_59:

Ah okay. Yes, your assumption was correct it does look like a backdoor read. I will have to do some more research on this. Thanks for the reply