Verification Academy

Topic	Replies	Views	Activity
VIP based verification UVM	2	147	November 27, 2025
Force a bunch of internal signals when there another particular signal goes high SystemVerilog assertion , System-Verilog , SVA	2	59	November 27, 2025
AHB Protocol: Data & Address Phase UVM AHB	0	117	November 25, 2025
Code coverage : Block Coverage Coverage	0	111	November 25, 2025
Display uvm_info including ps values UVM	7	86	November 23, 2025
Is there any way to merge two types of code coverage and show the total between them Coverage Coverage	2	114	November 21, 2025
SVA sequence re-triggers on multiple $fell events – rise_t not updating SystemVerilog	1	63	November 19, 2025
Continuous assignment between two inout SystemVerilog inout , continuous-assignment	3	58	November 19, 2025
Redefine a SV interface port direction in a modport SystemVerilog	2	87	November 19, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	130	November 17, 2025
Wait_for_state() in a static module doesn't work as expected UVM UVM-phase-methods , UVM_PHASE , phase , Cookbook-Phasing , UVM-phases , Related-to-UVM-phases , phasing , Phasing-within-a-static-entity	10	185	November 16, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	93	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	58	November 12, 2025
Resume simulation when any 2 threads out of 3 get completed within fork-join_any SystemVerilog SystemVerilog , fork-join_any	9	4308	November 12, 2025
Verifying synchronours fifo SystemVerilog	3	136	November 11, 2025
Question regarding followed by operator in SVA (#-# and #=# SystemVerilog SystemVerilog , SVA , SVA-Assertion	0	72	November 11, 2025
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	146	November 11, 2025
UVM RAL: How to execute register access without updating mirrored value? UVM UVM-RAL-UVM	1	106	November 8, 2025
VHDL Code Coverage - Generate Statements Coverage Coverage	2	75	November 6, 2025
Code debug help UVM	2	104	November 5, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	81	November 3, 2025
Why only ##1 (single delay operator) used in the case of multiple clock sequences? SystemVerilog SystemVerilog , assertion	2	689	November 3, 2025
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	5	3402	November 2, 2025
Migrating from IP to sub-system level UVM	2	112	November 2, 2025
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	96	November 2, 2025
Default value of enumarated varaible is first value of enum SystemVerilog	4	86	November 1, 2025
difference b/w nexttime and ##1 SystemVerilog assertion	1	73	October 31, 2025
Why ref bit and int doesnt Work in sampling but int andref bit Does Coverage	0	57	October 31, 2025
Paper: Understanding SVA Degeneracy SystemVerilog SystemVerilog , SystemVerilog-SVA	9	639	October 29, 2025
In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening? Coverage Coverage , questasim	2	60	October 29, 2025