Verification Academy

Topic	Replies	Views	Activity
Paper: Understanding SVA Degeneracy SystemVerilog SystemVerilog , SystemVerilog-SVA	9	617	October 29, 2025
In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening? Coverage Coverage , questasim	2	54	October 29, 2025
SVA with multiple Implication operators SystemVerilog	0	61	October 29, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	78	October 28, 2025
Function inside constraint SystemVerilog	1	103	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	124	October 27, 2025
is $fell(sig_a) true when sig_a from x to 0? SystemVerilog assertion , SVA	1	98	October 27, 2025
Question regarding latch behaviour SystemVerilog	1	79	October 27, 2025
Question on use of RAL model for System-On-Chip verification UVM	4	170	October 24, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	246	October 23, 2025
Understanding the throughout SVA SystemVerilog assertion , SVA-Assertion	11	1196	October 20, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	158	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	110	October 21, 2025
SV assertion related to req and grant SystemVerilog	2	112	October 18, 2025
Is there an alternative to sum() Constraint SystemVerilog SystemVerilog , Is-there-an-alternative-to-sum-Constraint	5	1901	October 19, 2025
Difference between -> and => in assertions SystemVerilog	5	198	October 19, 2025
How to use multiple sequences to override base test UVM	14	235	October 17, 2025
QuestaSim not loading design after restart -f SystemVerilog questasim	2	60	October 17, 2025
What operators constitute a multi-threaded sequence SystemVerilog SystemVerilog , SVA , multi-threaded-antecedent , multi-threaded-assertion	1	82	October 16, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	106	October 16, 2025
Clarification on sequence execution flow UVM cookbook figure UVM	6	87	October 16, 2025
$xm_force isnt working to force tb signals using hierarchical paths SystemVerilog	2	95	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	96	October 15, 2025
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	1	90	October 15, 2025
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	5	106	October 12, 2025
Need clarification on static method and non static method SystemVerilog SystemVerilog , non-static-method , static-method	11	4346	October 12, 2025
Coverpoint for groups of address SystemVerilog Coverage	1	62	October 10, 2025
Getting the virtual interface in the test class or in the agent? UVM	1	71	October 9, 2025
Protected registers behavior implementation with RAL UVM UVM	1	77	October 8, 2025
Query on Register wr/rd verification by taking security state into consideration UVM RAL	2	68	October 8, 2025