Get a Head Start on the New UVM Standard
Tom Fitzpatrick - Mentor Graphics
The newest version of UVM is coming soon from the IEEE. This new version will be based on UVM1.2, but there will be some changes. This session will discuss in detail what these changes are and discuss how they'll impact current UVM users, also fill you in on the latest happenings in the UVM committee. To help get you up and running in UVM more quickly, we'll also introduce the UVM Framework, which will dramatically shorten the time it takes to create your UVM environment and incorporate Mentor Verification IP to support a wide variety of standard protocols into your testbench.
SystemVerilog Assertions - Bind files & Best Known Practices
Cliff Cummings - Sunburst Design
SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. 13 years of professional SVA usage strongly suggests that Best Known Practices use bindfiles to add assertions to RTL code. This presentation will also show assertion coding guidelines that help reduce assertion coding effort, assertion coding mistakes and assertion coding frustration.
UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs
Gordon Allan - Mentor Graphics
Is your UVM testbench draining your productivity? Complexity pain and difficulty figuring out what's going on?
- Learn how to solve the top 10 common UVM bringup issues in areas such as the config_db, the factory, and sequence execution.
- Find out how to navigate complex UVM environments, quickly find your way around the code, whether your own or inherited.
- See what's going on in your testbench - how to debug dynamic class activity in SV/UVM alongside RTL signals.
Back to the Stone Ages for Advanced Verification
Neil Johnson - XtremeEDA
Modern development approaches are leaving quality gaps that advanced verification techniques fail to address... and the gaps are growing in spite of new innovation. It's time for a fun, frank and highly interactive discussion around the shortcomings of today's advanced verification methods. We'll talk present day. We'll also go waaaay back to the stone ages of verification to revisit the importance of techniques like unit testing as highly productive additions to any modern development approach.
Verification IP and Memory Models Improve Productivity and Reduce Risk
Mark Olen - Mentor Graphics
Many designs incorporate standard interfaces, such as ARM® AMBA®, DisplayPort™, DDR DRAM, Ethernet, Flash Memory, HDMI®, MIPI, PCIe®, USB and more, that can put a strain on the verification process. Building verification IP for these standards can be a complex process, and takes valuable time away from writing design-specific tests. This session illustrates how many companies are improving their productivity by moving to third-party verification IP and memory models, complete with protocol checks, coverage models, and compliance test suites.
Formal Verification Tips & Tricks for Fun & Profit
Doug Smith - Mentor Graphics
Join us to learn SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, simple tips to setup the analysis for rapidly reaching a solution, and benefiting from "coverage" in a formal context.
Get Ready for Portable Stimulus
Tom Fitzpatrick - Mentor Graphics
It sounds like an impossible task. How can you have a single stimulus description that can drive everything from a UVM test in simulation to C++ code in an emulator to a bare metal test post-silicon? The answer is the new Portable Stimulus standard being worked on in Accellera, but the question isn't "how can one specification be all things to everyone?" This session will clearly explain what Portable Stimulus is (and what it isn't), how the Portable Stimulus Working Group is tackling the problem, and what the solution is likely to be. Get the latest information about this exciting new frontier in functional verification from an expert who's been involved in the standard from its inception and learn how you'll be able to use it in your verification environment.
Verification Patterns: An Optimized Reusable Solution
Harry Foster - Mentor Graphics
Design patterns provide an optimized, reusable solution to many of today's engineering problems. Experience has shown that they are an effective tool for sharing best practices and building skills within a project team. However, one problem that has prevented the widespread adoption of design patterns within the verification community is a lack of an easily searchable library of patterns. In this session, we introduce the new Verification Academy Patterns Library and present pattern examples that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.
Orange is the New Black, Reset Verification is the New CDC
Joe Hupcey III - Mentor Graphics
The increase in reset signaling complexity is creating "reset domains" that can create metastability and signal reconvergence issues similar to the failures seen in asynchronous clock domain crossings (CDC) – which aren't addressable by RTL simulations. In this presentation we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.
Various Methods for Debugging Software in Emulation
Russ Klein - Mentor Graphics
The Mentor Veloce emulation platform combined with the Questa verification solution can run designs in RTL orders of magnitude faster than simulation alone. As a result, emulation is used to execute verification runs that would be otherwise impossible in logic simulation. Often these verification runs include some software executing on the design – as software is taking an increasing role in the functionality of a System-on-Chip (SoC). With significant software being executed in the context of the verification run, there needs to be some way to debug it. This session covers the various methods provided for debugging software in the context of emulation.
Debug Data API Update
Dave Rich - Mentor Graphics
The Debug Data API is a modernized way to share waveform information than VCD. If VCD still works for you, don't worry, we are not doing anything to change that flow. The industry has invested decades in access methods for live simulation, but common post simulation results data access has been generally limited to ASCII file dumps in the VCD or eVCD format that have reached their end-of-life. We are looking to extend and augment a traditional live simulation vpi-scheme with one that works for post simulation run datasets as well. You are invited to join us to get an update on the current status of the Debug Data API development and projected timeline of support. We will demonstrate use of the Debug Data API to create debug applications written in C/C++ running on early prototypes from Mentor and Cadence.
Verifying Safety-Related Systems
Mike Bartley - TVS
The traditional environments for safety-related hardware and software such as avionics, rail and nuclear have been joined by others (such as automotive and medical devices) as systems become increasingly complex and ever more reliant on embedded software. In tandem, further industry-specific safety standards (including ISO 26262 for automotive applications and IEC 62304 for medical device software) have been introduced to ensure that hardware and software in these application areas has been developed and tested to achieve a defined level of integrity. In this presentation, we will be explaining some of these changes and how they can be implemented. We'll be covering the impact of safety standards on requirements: how they need to be defined; how they need to be managed; and how they need to be mapped to tests to demonstrate that they have been implemented correctly. We will also explore how techniques such as static analysis and automated dynamic testing provide a foundation for a verification strategy that will ensure compliance with safety standards.
Specification to Realization flow using ISequenceSpec™ and Questa® inFact
Anupam Bakshi - Agnisys, Inc.
Using an Ethernet Controller design, we show how complete verification can be done in an automated manner, saving time while improving quality. Integration of two tools will be shown. InFact creates tests for a variety of scenarios which is more efficient and exhaustive than a pure constrained random methodology. ISequenceSpec forms a layer of abstraction around the IP/SoC from a specification.
Streamlining Formal Verification Process
Xiushan Feng & Ram Narayan - Oracle Corp.
With the capability to attack large circuits for high coverage, formal verification usage has been growing significantly over the past decade. Many companies have built specialized formal verification teams to deploy formal methods within design flows. This presentation describes how to effectively enable formal verification process within your own organization. This includes a flow that simplifies test bench creating, speeds up runtime, and standardizes formal result reviewing. By applying this flow, our team aggressively pushed the use of formal tools to all design units. We use real-life examples to show you how to make formal verification more streamlined in your own flow!
Using a Chessboard Challenge to Discover Real-world Formal Techniques
Vigyan Singhal & Prashant Aggarwal - Oski Technology
In December 2015, Oski challenged formal users to solve a chessboard problem. This was an opportunity to show how nifty formal techniques might be used to solve a fun puzzle. Design verification engineers from a variety of semiconductor companies and research labs participated in the contest. The techniques submitted by participants presented a number of worthy solutions, with varying degrees of success. In all cases, formal techniques were needed fight formal complexity. In this talk we describe the puzzle, and some of the techniques, all of which are relevant to real-world ASIC designs. Techniques included case-splitting, symmetry reduction, assume-guarantee and disabling lower proof depths. We will also describe the winning solution.
Fireside Chat Verification Panel Discussion
Harry Foster - Mentor Graphics
Join the Verification Academy Subject Matter Experts as they field questions about UVM, Portable Stimulus, SystemVerilog, Emulation, Testbenches, Standards, Training, High Level Synthesis, Languages and more!.
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