Portable Stimulus: Is It Revolution or Evolution?
Tom Fitzpatrick - Mentor, A Siemens Business
Many claim the new Portable Test and Stimulus Standard. (PSS) from Accellera will ignite the next revolution in SoC and Electronic System functional verification. Revolutionary innovation seeks to adapt the world to new and better ideas; yet it can be disruptive, expensive and produce unpredicted outcomes[1]. On the surface PSS seems the same. It brings a new methodology in defining test benches that has great promise in productivity and verification quality, but will require the adoption of new tools, a re-education of verification engineers and a retooling of verification infrastructure – all potentially costly endeavors. What if there was a way to adopt this revolutionary innovation incrementally? Leveraging existing verification infrastructure, including existing UVM/SV test benches and verification IP; enabling the benefits of PSS incrementally as the workforce gets up to speed. Come hear how Reuse can be the Evolution that enables the PSS Revolution.
First Pass Success Depends on Holistic Planning that Includes Formal
Harry Foster - Mentor, A Siemens Business
Successful verification depends on methodical verification planning combined with systematic verification processes. The key to success is the verification testplan, but all too often such plans focus only on a coverage-centric approach without considering the strengths of technologies and methodologies beyond constrained-random simulation. The addition of formal verification is one example of a holistic approach to strategic verification planning. Certainly formal can be used to prove an ad hoc set of assertions focused on high risk, high complexity functionality; but such a narrow application of this technology limits the significant benefits that automated formal apps and a formal property checking test bench can provide. In this talk you will learn how to integrate multiple formal solutions into a holistic planning process and a metric-driven verification work-flow.
When Are You Done Running CDC?
Chris Giles - Mentor, A Siemens Business
Poorly designed clock-domain crossings kill chips. They kill products. They slip through simulation, are elusive in hardware validation, and can masquerade as other issues. The designer is held accountable for the results, and if not careful can be left in the lab for long nights of frustrating debug - or worse. Like the age-old verification question "how do you know when you're done testing?" It's fair to ask the designer "how do you know when to stop looking for CDC issues?" But in this era of many clock and power domains, third party or legacy IP and intense PPA pressure, rigorous design and reviews are simply not enough. So how much CDC checking is enough? In this session we will discuss how to ensure that all CDCs are solid.
End-to-end Functional Safety for ISO 26262
Bryan Ramirez - Mentor, A Siemens Business
Combining Mentor’s acquisition of Austemper Design Systems with existing Mentor and Siemens technologies, Mentor Safe IC provides the most comprehensive functional safety solution to bring increased automation for the entire IC functional safety flow. This session will provide an overview of Mentor Safety IC and how it can help increase your efficiency, shorten development cycles and reduce risk.
Debugging Your Design in a Heterogeneous Environment
Rich Edelman - Mentor, A Siemens Business
Designs are dramatically more complex today, often consisting of huge subsystems and IP (both legacy and acquired). The verification process of these complex designs involves Simulation, emulation, static, formal, UVM, power-aware, etc... Users debugging these complex heterogeneous environments are looking for a unified debug solution that will present data in context and make engines/technologies transparent. In this session we will discuss Mentor's solution to address debug needs of today's complex environment using Questa® Visualizer Debug.
Stay Ahead of the Curve: Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity
Tom Fitzpatrick - Mentor, A Siemens Business
The Universal Verification Methodology (UVM) continues to be the most popular and still fastest-growing methodology for describing modular coverage-driven constrained-random transaction-level testbenches. However, as designs continue to grow in size and protocols continue to grow in complexity, we may need to consider new tools and techniques to keep UVM at the forefront of functional verification. In this session, we will discuss the requirements for protocol-specific verification in a UVM environment and show how the Questa Verification IP (QVIP) library was developed to provide UVM users with pre-packaged verified components for use in their environments to accelerate testbench development and provide greater debug visibility and control. We will also discuss the new QVIP Configurator making it simple to customize QVIP components to easily fit your verification environment. We will close with an overview of how you can use Portable Stimulus to leverage the built-in infrastructure in QVIP and your UVM environment to realize truly coverage-driven scenario-level functional coverage to keep you ahead of the productivity curve.
SoC Verification Problems From Early Software To System Implementation
Gordon Walker - Mentor, A Siemens Business
The software-defined systems has arrived. In practice, it means that software applications are driving the future of SoC architectures. Solutions need to enables exploration, optimization, and validation of complex vertically integrated, application-driven, HW/SW systems.
Emulation ↔ Prototype - What’s Eating Your Productivity?
Stephen Bailey - Mentor, A Siemens Business
Hardware accelerated verification & validation are supposed to be fast. Yet, productivity begins before the first cycle is run. HW enables performance, performance enables productivity but doesn't guarantee it. Where are the productivity hurdles and traps? What is the impact to your productivity if planning and solutions do not provide what you need to maximize your productivity? These are the questions which we will explore to enable you to focus on productivity before and beyond the cycles.
Questa inFact PSS-Infused Apps Make the Most of Your UVM
Tom Fitzpatrick - Mentor, A Siemens Business
Modeling scenarios with the new Portable Test and Stimulus language (PSS) enables users to focus on the high-level requirements of what they need to test, and use automation to create specific valid tests and make those tests portable across a range of verification environments. Wouldn’t it be great if we could bring this same ability to focus on what we want to test instead of how to our existing SystemVerilog UVM testbench environments? We most certainly can by adding PSS-created tests to our UVM testbenches, but there’s an even easier way! inFact’s PSS Apps for SystemVerilog leverage the same core algorithms that enable PSS users to focus on what they want to test, not how. But, the inFact PSS Apps read in existing SystemVerilog classes and covergroups, allowing you to make the most of your existing testbench, while also increasing your verification productivity. Come see how the inFact PSS Apps can help you create correct-by-construction SystemVerilog covergroups, analyze your constraints pre-simulation, and generate efficient stimulus for coverage closure and bug hunting.
Improving Verification Throughput of Complex Mixed-Signal ICs with High-Level Model Abstractions
Sathish Balasubramanian - Mentor, A Siemens Business
Mixed-signal designs (such as multi-slope/ΔΣ ADCs, phase locked loops, high-speed I/O links, etc.) usually involve close interactions between analog and digital sub-circuits. However, digital blocks (such as digital filters, phase frequency detectors, frequency dividers or control logic) can consist of a large number of transistors – much larger than their analog counterparts. These digital circuits severely slow down the simulation, while simulation results may only capture unnecessarily accurate details of digital blocks. Since for digital circuits, an RTL representation, or even just a finite state machine model, can describe circuit behaviors well enough, it is preferable to use these high-level models during simulations of the whole system. In this session we describe how Mentor’s Symphony verification platform addresses the need of such mixed signal methodology and improve simulation throughput for faster TTM.
Streamlining Plan & Requirements Driven Verification
Darron May - Mentor, A Siemens Business
Being able to author a test (verification) plan in a collaborative team environment is an important aspect of both Plan Driven and Requirements Driven methodologies. Once the test plan is defined, the common verification process is driven by ensuring that all the design features are being successfully tested. This is achieved by linking the tests and coverage model references defined within a test plan to the results of verification. The connection from the test plan to the design specification can be loosely bridged by the Verification Engineer. Alternatively, a requirements management system can hierarchically decompose system requirements through to hardware/software requirements, and onto test plans with verification results. This detailed level of traceability is a requirement of functional safety standards such as ISO 26262 or DO-254. There may also be demands for traceability and audit between the design requirements and the VHDL/Verilog implementation. Ideally a smooth path should exist between the two methodologies, enabling a project to migrate from Plan Driven to Requirements Driven when it becomes necessary to fulfill the demands of safety critical standards. As well, an ideal solution should be agnostic to allow different data formats and tools to be supported. This session will highlight that Siemens and Mentor are in a great position and can offer a single solution to address both Plan Driven and Requirements Driven verification methodologies.
An Emulation Strategy for Artificial Intelligence and Machine Learning Devices
Vijay Chobisa - Mentor, A Siemens Business
The emergence of Artificial Intelligence is the “next big thing” in the overall economy and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session. Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of machine learning benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average power. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of ASICs targeted for AI.
DFT Enablement for AI Devices
Geir Eide - Mentor, A Siemens Business
Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
Methodology to Debug Real Number Model Boundary Scenarios using Symphony & Questa Visualizer Debug Environment
Sumit Vishwakarma - Mentor, A Siemens Business
Real Number Models (RNM) empowers verification engineer to describe an analog block as a discrete floating point model, and enable it to simulate in a digital solver at near-digital simulation speeds. In a design, when a RNM block interacts with a standard logic block, signal conversion happens and “real to logic” and “logic to real” boundary elements are inserted by digital solver. As the design hierarchy and complexity grows, the number of interaction increases and it becomes cumbersome to debug these boundary conversions. In this session we will dive into a simple scenario and demonstrate how you can take advantage of Symphony and the Visualizer Debug Environment to debug RNM boundary scenarios in case of a functional failure.
UVM and Portable Stimulus: A Match Made in Heaven
Tom Fitzpatrick - Mentor, A Siemens Business
With the advent of the new Portable Test and Stimulus standard from Accellera, one of the most asked questions we hear is, "will Portable Stimulus replace UVM?" The answer is absolutely not. Portable Stimulus was conceived from the ground up to take advantage of UVM as one of the possible realization platforms for which tools may generate tests. This session will look at the PSS-UVM relationship and help attendees understand this important and powerful relationship.
Formal Bug Hunting with “River Fishing” Techniques
Harry Foster - Mentor, A Siemens Business
Bugs happen when multiple events collide in uncommon scenarios. Our methodology leverages your functional simulation activities and starts formal verification from interesting “fishing spots” in the simulation traces. We will show where the most interesting “fishing spots” are, and explain how formal engine health is used to prioritize and guide the process.
Auto-Generation of Implementation-Level Sequences for PSS
Anupam Bakshi - Agnisys
PSS aims to help users describe the high-level test intent and generate code for various verification platforms. In order to further enhance portability, by design PSS avoids the implementation details. This means users have to manually code long and complex hierarchical test sequences for IP and SoC tests in different languages such as C, SystemVerilog or CSV. In this presentation, we will show a unique solution based on the integration of iSequenceSpec with Questa inFact. The implementation-level sequences can be captured by the user in pseudo code using a Python text-based environment and generate the target sequence code to be used for simulation, emulation, firmware tests and post-silicon validation. The solution synchronizes multiple SoC groups to work from a golden spec - critical to today’s SoC projects. With the ability to parse register and memory maps in SystemRDL, IP-XACT or CSV, users are able to exercise the hardware/software interface through register read/writes and bus transaction-level messages.
RISC-V Core & SoC Compliance, Verification, Customization
Larry Lapides - Imperas Software Ltd.
The open instruction set architecture of RISC-V provides significant innovation freedoms such as easy addition of custom instructions and extensions, but also puts more demands on design teams in terms of compliance checking and verification of the cores. This presentation will discuss the balancing act for RISC-V, and go through flows, tools and models for compliance, verification and adding custom instructions using various case studies.