SoC Verification Problems From Early Software To System Implementation
10:00 AM | Gordon Walker - Mentor, A Siemens Business
The software-defined systems has arrived. In practice, it means that software applications are driving the future of SoC architectures. Solutions need to enables exploration, optimization, and validation of complex vertically integrated, application-driven, HW/SW systems.
Emulation ↔ Prototype - What’s Eating Your Productivity?
11:00 AM | Stephen Bailey - Mentor, A Siemens Business
Hardware accelerated verification & validation are supposed to be fast. Yet, productivity begins before the first cycle is run. HW enables performance, performance enables productivity but doesn't guarantee it. Where are the productivity hurdles and traps? What is the impact to your productivity if planning and solutions do not provide what you need to maximize your productivity? These are the questions which we will explore to enable you to focus on productivity before and beyond the cycles.
Selecting the Most Productive SoC Design Verification Techniques
12:00 PM | Paul Williams & Rama Lakamsani - Arm®
We describe how ARM Partnership Enablement Group and Mentor Consulting Division are working together overcome the obstacles which limit the ability of our partners to optimize their verification methodology. We provide guidance to enable verification managers to compare their existing verification approach with the state of the art and to determine the most valuable areas for change.
IP Development Methodology on HYCON
1:00 PM | HJ Woo - Samsung
The main purpose of HYCON methodology is to enable both SW/HW co-design and co-verification prior to building matured SoC, thus contributing to the reduction of total development period for mobile APs by securing early-verified SW/HW IP. The proposed methodology adopts co-emulation of QEMU simulation and HW emulation. Most of the IPs such as CPU, eMMC, CLCD and peripherals, which are used frequently for Android platform boot-up, are allocated to the QEMU simulation side, which maximizes run-time performance of SW. The only target IPs and memory subsystem are allocated to HW emulator side to help start SW development with RTL (Register Transfer Level) design. Except the target IP, all of IPs are the QEMU library models which are already verified. It is fast to bring-up the Platform including compilation and running time. Application results show that booting an Android platform can be completed within 10 minutes on the proposed methodology, and show that SW driver and IP’s firmware are successfully developed and validated with RTL before the silicon based development board is ready.
Have Your Cake and Eat it Too: Make the Most of your UVM Environment for Coverage Closure AND Bug Hunting with PSS Infused Apps for SystemVerilog
2:00 PM | Tom Fitzpatrick - Mentor, A Siemens Business
Modeling scenarios with the new Portable Test and Stimulus language (PSS) enables users to focus on the high-level requirements of what they need to test, and use automation to create specific valid tests and make those tests portable across a range of verification environments. Wouldn’t it be great if we could bring this same ability to focus on what we want to test instead of how to our existing SystemVerilog UVM testbench environments? We most certainly can by adding PSS-created tests to our UVM testbenches, but there’s an even easier way! inFact’s PSS Apps for SystemVerilog leverage the same core algorithms that enable PSS users to focus on what they want to test, not how. But, the inFact PSS Apps read in existing SystemVerilog classes and covergroups, allowing you to make the most of your existing testbench, while also increasing your verification productivity. Come see how the inFact PSS Apps can help you create correct-by-construction SystemVerilog covergroups, analyze your constraints pre-simulation, and generate efficient stimulus for coverage closure and bug hunting.
Improving Verification Throughput of Complex Mixed-Signal ICs with High-Level Model Abstractions
3:00 PM | Sathish Balasubramanian - Mentor, A Siemens Business
Mixed-signal designs (such as multi-slope/ΔΣ ADCs, phase locked loops, high-speed I/O links, etc.) usually involve close interactions between analog and digital sub-circuits. However, digital blocks (such as digital filters, phase frequency detectors, frequency dividers or control logic) can consist of a large number of transistors – much larger than their analog counterparts. These digital circuits severely slow down the simulation, while simulation results may only capture unnecessarily accurate details of digital blocks. Since for digital circuits, an RTL representation, or even just a finite state machine model, can describe circuit behaviors well enough, it is preferable to use these high-level models during simulations of the whole system. In this session we describe how Mentor’s Symphony verification platform addresses the need of such mixed signal methodology and improve simulation throughput for faster TTM.
Auto-Generation of Implementation-Level Sequences for PSS
4:00 PM | Anupam Bakshi - Agnisys
PSS aims to help users describe the high-level test intent and generate code for various verification platforms. In order to further enhance portability, by design PSS avoids the implementation details. This means users have to manually code long and complex hierarchical test sequences for IP and SoC tests in different languages such as C, SystemVerilog or CSV. In this presentation, we will show a unique solution based on the integration of iSequenceSpec with Questa inFact. The implementation-level sequences can be captured by the user in pseudo code using a Python text-based environment and generate the target sequence code to be used for simulation, emulation, firmware tests and post-silicon validation. The solution synchronizes multiple SoC groups to work from a golden spec - critical to today’s SoC projects. With the ability to parse register and memory maps in SystemRDL, IP-XACT or CSV, users are able to exercise the hardware/software interface through register read/writes and bus transaction-level messages.
Plan Driven and Requirements Driven Verification
5:00 PM | Neil Hand - Mentor, A Siemens Business
Being able to author a test (verification) plan in a collaborative team environment is an important aspect of both Plan Driven and Requirements Driven methodologies. Once the test plan is defined, the common verification process is driven by ensuring that all the design features are being successfully tested. This is achieved by linking the tests and coverage model references defined within a test plan to the results of verification. The connection from the test plan to the design specification can be loosely bridged by the Verification Engineer. Alternatively, a requirements management system can hierarchically decompose system requirements through to hardware/software requirements, and onto test plans with verification results. This detailed level of traceability is a requirement of functional safety standards such as ISO 26262 or DO-254. There may also be demands for traceability and audit between the design requirements and the VHDL/Verilog implementation. Ideally a smooth path should exist between the two methodologies, enabling a project to migrate from Plan Driven to Requirements Driven when it becomes necessary to fulfil the demands of safety critical standards. As well, an ideal solution should be agnostic to allow different data formats and tools to be supported. This session will highlight that Siemens and Mentor are in a great position and can offer a single solution to address both Plan Driven and Requirements Driven verification methodologies.
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