Portable Stimulus is Here! (Almost)
Tom Fitzpatrick - Mentor, A Siemens Business
The new Portable Stimulus Standard being worked on in Accellera promises to provide the next leap in verification productivity needed to support our ever-growing SoC verification challenges. Portable Stimulus addresses these challenges by providing a single specification of test intent and coverage at a higher level of abstraction, allowing tools to generate target-specific implementations of the test for the desired platform(s) and freeing up the verification team to focus on what should be tested instead of wasting time and effort recreating the same tests in different languages and formats throughout a project. This session will provide an overview of the upcoming Standard and clarify the expected use models for this exciting technology. We'll also share some details about the current capabilities of Mentor's portable stimulus solution, Questa inFact, and what you can expect from Questa inFact once the standard is officially released.
Add Unit Testing to Your Verification Toolbelt
Neil Johnson - XtremeEDA
Constrained random verification is a tool, like a hammer. And for engineers that use it exclusively, everything starts to look like a nail. I mean everything. It's to the point we have server rooms full of hammers and entire teams of engineers smashing everything in sight. Day and night. Repeatedly. It's a good tool. But as the only tool, constrained random can be chaotic and unproductive. Unit testing is a practical, tactical development practice that makes constrained random verification more predictable and more productive. It's easy to get started, accessible to design and verification engineers alike and the quality benefits are real. We'll look at where unit testing fits into our functional verification paradigm, how to start unit testing using SVUnit and the gains we can expect as a result.
SystemVerilog Object Oriented Programming Basics used in UVM Verification
Dave Rich - Mentor, A Siemens Business
Object Oriented Programming (OOP), Design Patterns, and the UVM are technologies aimed at writing more manageable and re-usable code. Adopting these skills may seem like quite an overwhelming task as many hardware verification engineers do not have much of a software background. This presentation give you some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.
Applying Big Data Analytics to Today's Functional Verification Challenge
Harry Foster - Mentor, A Siemens Business
During the design process a tremendous amounts of simulation data and metrics are generated. This potentially presents the opportunity to uncover hidden insights by learning from historical relationships and trends in the data. In this talk we explore the application of big data analytics to address today's growing functional verification challenges.
C'mon ... Quit Screwing-Up the UVM $display Command!!
Cliff Cummings - Sunburst Design
UVM Messaging macros offer a powerful, run-time selection capability that should be exploited in every UVM verification environment but verification engineers do not know how to properly use these capabilities. This presentation will show proper usage of UVM Messaging macros and propose messaging enhancements beyond current UVM capabilities.
Emerging Trends in AMS Verification Methodology for Automotive & IoT Devices
Sathish Balasubramanian - Mentor, A Siemens Business
Automotive and IoT applications require complex analog/mixed-signal (AMS) devices with an ever-increasing analog content coupled to traditional digital applications. These devices pose challenges and additional requirements on existing AMS verification tools and methodology. This talk would provide an overview of these added complexities on AMS verification and how to successful tackle these verification challenges in predictable and efficient ways.
Breaking the Speed Limits of SoC Verification
Gordon Allan - Mentor, A Siemens Business
In this session, you will learn more about common (block-, subsystem, & SoC-level) verification flows in use today and how to improve productivity by optimizing best practices of the verification flow design. In addition, you will be introduced to Mentor's Questa® Simulator and how it can provide the highest performance across the verification flow.
A Fresh Look at UVM and the New UVM Cookbook
Tom Fitzpatrick - Mentor, A Siemens Business
With the approval of the IEEE 1800.2 UVM Standard, it's time to take another look at UVM. This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard. We will also highlight some key changes we're making in the UVM Cookbook to help you set up your testbench to maximize reuse throughout your verification flow, especially if you want to reuse your UVM testbench in all available engines including emulation. We will also see how the UVM Framework will automatically build your environment according to these new guidelines, letting you get a UVM environment up and running in just a few hours. Even if you've been using UVM for years, we'll show you how you can be even more efficient and portable in creating your UVM environment.
Accelerating UVM-based Verification from Simulation to Emulation
Vijay Chobisa - Mentor, A Siemens Business
One of the biggest challenges for any chip design is to deliver a high-quality product, and at the same time, meet the project schedule. As projects iterate through debugging cycles, long turnaround time can become costly in terms of project schedule. This issue can be alleviated with a significant speed up in simulation. This is where emulation fits in. In our case, we mapped the design onto the Veloce emulator and made some modifications to the test bench environment, which is primarily UVM. This accelerated our overall verification process allowing us to run many more cycles using considerably more complex tests. In this session, we will look at the major issues encountered, lessons learned, and the final results of migrating a complex ASIC with a UVM-based environment to the Veloce emulator.
Debugging Trends, Challenges, and Novel Solutions
Harry Foster - Mentor, A Siemens Business
The debugging task is both unpredictable and time consuming. Anything a project can do to optimize the debugging task is a win for the organization. This talk explores the latest trends in debugging, and then discusses new solutions to the debugging challenge.
Staying Competitive by Evolving Your FPGA Verification Methodologies
Bryan Ramirez, Mentor, A Siemens Business
FPGA vendors continue to innovate creating new ways for FPGA users to more efficiently design into today's increasingly complex FPGAs. This has created a widening gap between design abstraction and verification of these FPGAs in which traditional verification approaches come up short. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive. Unfortunately, they don't always know where to start or find the cost/risk to great to embark on. In this session you will learn about themes in the FPGA industry that are pushing the need for advanced verification, understand how other FPGA users in industry are adapting to this and see how taking a new look at your verification methodologies can help you build higher quality, on-time products enabling you to be more competitive in today's evolving FPGA market.
How Formal Reduces Fault Analysis for ISO 26262
Doug Smith - Mentor, A Siemens Business
The ISO 26262 standard defines straightforward metrics for evaluating the "safeness" of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult because evaluating every possible fault is impractical on the size of today's designs. Formal verification tools have an advantage over other approaches because formal tools have the unique ability to trace cones of influence and eliminate large numbers of irrelevant faults in a process known as fault pruning. With a significantly reduced fault list, fault analysis can be performed exhaustively with formal techniques like sequential logic equivalency checking (SLEC), or coupled together with fault simulation and emulation for checking software based safety mechanisms. Formal tools provide unique capabilities that are essential for any automotive functional safety flow.
Verification and Validation in the SoC Age
Stephen Bailey - Mentor, A Siemens Business
Functional verification is the biggest business and technical challenge in delivering complex SoC's and systems on time and within budget. Although we manage the process by dividing the flow between into hardware and chip verification and chip and system-level validation, the ability to cover the complete flow with fast engines, intelligent stimulus, analysis and debug solutions and a strong infrastructure of VIP and methodology has become the key to project success. This session will discuss how an Enterprise Verification Platform is delivering performance, quality and overall productivity throughout the verification and validation flow to get you to success faster.
Why Gate-Level CDC Is Needed (Even After RTL CDC Closure!)
Dominic Lucido - Mentor, A Siemens Business
Increasing usage of multi-clocking architecture to meet high performance and low power requirements of the modern SOCs makes clock-domain crossing (CDC) verification a critical step in design verification cycle. CDC verification is not only necessary on RTL; as the available "bandwidth" at the 28 nm nodes and below decreases, RTL-to-Gate synthesis can create glitches and CDC issues that are unobservable by CDC analysis at the RTL level that can lead to silicon failure. However, attempting CDC closure on gate-level designs with an RTL-level flow results in a very high setup effort, analysis scalability challenges, and an unwelcome volume of low quality, "high noise" results. In this presentation, we review the causes of these challenges and introduce an automated approach to overcome these difficulties. The proposed methodology is based on leveraging inputs from RTL CDC verification to automate and accelerate gate-level CDC verification closure with very "low noise" results.
Verification IP & Memory Models Improve Productivity & Reduce Risk
Mark Olen - Mentor, A Siemens Business
Many designs incorporate standard interfaces, such as ARM® AMBA®, DisplayPort®, DDR, CAN, Ethernet, Flash Memory, HDMI®, MIPI, PCIe®, USB and more, that can put a strain on the verification process. Building verification IP for these standards can be a complex process, and takes valuable time away from writing design-specific tests. This session illustrates how many companies are automating the development of their testbench by moving to third-party verification IP and memory models, complete with protocol checks, coverage models, and compliance test suites.
Low-Power Design using High-Level Synthesis for Automotive Image Sensor
Marc Schmitz - ST Micro
An image signal processor (ISP) is used to post-process data coming from the pixel array, applying a wide range of algorithms to the captured picture, such as defect correction, HDR merge, and noise reduction. Area and low-power are key differentiators, and a robust design flow is needed to meet ISO 26262 requirements. In this session, STMicroelectronics details how C++ templates and Catapult® tools are used to design the ISP building blocks, enabling maximum flexibility and significantly accelerating the development of the products. They also present the associated verification flow, based on a generic UVM environment, that takes benefit from HLS and ensures a high design quality. Finally, they show how this fast design method is compliant with the ISO 26262 automotive standard.
Formal Verification - Come on Man, Go For It!
Video 
| Slides 
John Aynsley - Doulos
The tool vendors tell us that formal verification is now ready for general use, and you don't need a PhD to use it. Meanwhile, big companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps". So, what is the truth of the matter? Can non-specialist engineers become productive with formal?
Architectural Formal Verification: A 3-Step Guide
Video | Slides
Kamal Sekhon, OSKI Technology
Design requirements such as coherency, absence of deadlock and security must be verified at the system level. Traditionally, we used RTL verification to do this, but coverage at that level is insufficient and bugs are found late in the design cycle. Architectural formal verification provides exhaustive analysis and can be deployed very early in the design process, before any RTL code is written.
Selective-hardening: Low-cost Soft-error Solution for Automotive
Video | Slides
Jamil Mazzawi - Optima DA
Transient random faults ("soft errors") are becoming a major challenge for safety-critical designs like Automotive IC's. Using redundancy or lock-step requires 2x and 3x duplications of IPs, impacting cost, power and area. Other alternatives are complex to implement. We present a automated selective hardening methodology that exceeds the required ISO-26262 safety-levels, is easy to implement, and minimizes cost, power and area penalties.
SeeCubic: An Ultra-D Business Enabler by Catapult HLS – It's Technology, But Not as you Know it
Video | Slides
Eric Leenman - SeeCubic
Ultra-D technology provides a solution for glasses-free autostereoscopic displays that can be used in any display application. Real-time conversion of 2D or 3D (left/right) signals to the Ultra-D format is a key component of the Ultra-D implementation. This conversion is based on innovative depth estimation using our patented proprietary algorithms. When our business development team requested the development of an IP block for this function, we were facing a Catch-22 situation. How do we design an IP block that is suitable for IC integration without information on the semiconductors technology? Furthermore, how do we design it for multiple technologies and enable integration in multiple products with different on-chip infrastructures? In this presentation, we show how Catapult® High-Level Synthesis (HLS) development methodology has enabled this IP block development. We will also illustrate how we executed the project with a relatively small team, resulting in a complete FPGA-based validation platform. And finally, we will share some unexpected lessons and reflect on key organizational success factors.
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