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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Verification Academy at DAC 2015

Verification Academy at DAC 2015

The Verification Academy focuses on key aspects of advanced functional verification, including: UVM/OVM, Coverage, Assertion-Based Verification, Verification Management, CDC and Formal Verification, Acceleration, FPGA Verification, and more. At this year's Verification Academy Booth, we lined up an excellent set of industry experts to speak - covering a wide range of topics of advanced functional verification techniques. For those of you not able to attend live, we recorded the sessions to make them available to all our members. You will need to login with your Full Access account to view or download the booth theater session videos and slides below.

Need to become a member?

This year we've planned unique solution focused days that you will not want to miss:

  • Debug
  • Industry Standards (UVM, UPF, Portable Stimulus & SystemVerilog), and FPGA Trends
  • Formal Verification

  DAC 2015

 

Debug Sessions

Trends in Debugging: From Challenges to Solutions

Video | Slides

Harry Foster - Mentor Graphics

Without a doubt, debugging is the biggest bottleneck encountered in today's verification flow. As the saying goes, "Sometimes it pays to stay in bed in Monday, rather than spending the rest of the week debugging Monday's code." This DAC Verification Academy theater session focuses on today's verification trends with an emphasis on debugging challenges, opportunities, and emerging solutions.

Broad & Flexible Silicon Debug Visibility

Video | Slides

Stephen Bailey - Mentor Graphics

Whether it is an FPGA prototype, FPGA design or ASICs, debugging silicon is difficult and usually tedious. Key silicon debug productivity challenges include the breadth and depth of visibility into silicon, especially when debugging software and system functionality. These are closely followed by the ease in instrumenting the design and configuring the instruments at run time. This session will show how to achieve unprecedented silicon visibility and debug productivity.

Software Debug on Veloce

Video | Slides

Jim Kenney - Mentor Graphics

The Mentor Veloce emulation platform combined with the Questa verification solution can run designs in RTL orders of magnitude faster than simulation alone. As a result, emulation is used to execute verification runs that would be otherwise impossible in logic simulation. Often these verification runs include some software executing on the design – as software is taking an increasing role in the functionality of a System-on-Chip (SoC). With significant software being executed in the context of the verification run, there needs to be some way to debug it. This session covers the various methods provided for debugging software in the context of emulation.

Next Generation Debug Experience with Visualizer Debug

Video | Slides

Vahid Naraghi - Brocade

Brocade Communications Systems, as an innovative networking HW and SW technology corporation, understand the value of being able to perform deep analysis and have sufficient visibility of the data and activity in their network. The same goes for debug of their complex silicon projects. We will show how our design verification team moved up to Mentor's Visualizer Debug Environment as the design entered a complex phase of development and we required a robust, stable, feature-rich debugging tool. The team looked for a debug solution that had a small memory footprint, tight simulator integration, high capacity and performance. We show how Visualizer solved those problems and provides post-simulation visibility of class member values as if running live on the simulator.

Evolution of Debug

Video | Slides

Gordon Allan - Mentor Graphics

The debug activity takes a significant proportion of any design or verification engineer's time and there is much we in the Design Automation industry can do to improve individual and team productivity in this area. It starts with putting ourselves in the users' shoes and designing a complete solution, not just 80% of a solution. Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.

UVM Message Display Commands Capabilities, Proper Usage and Guidelines

Video | Slides

Cliff Cummings - Sunburst Design

UVM message display commands offer great flexibility in printing of UVM messages, but their usage is frequently misunderstood. In fact, the first printings of two respected UVM texts released in 2013 either incorrectly describe UVM verbosity, incorrectly use UVM verbosity settings in examples, or both. Many new users incorrectly assume the built-in verbosity settings represent printing priority, but this is exactly backwards from reality. It is time to set the record straight, give a correct description of UVM verbosity and suggest important UVM verbosity usage guidelines. This presentation details strategies and guidelines for proper usage of UVM display commands.

An Agile Evolution in SoC Verification

Video | Slides

Neil Johnson, XtremeEDA & Harry Foster - Mentor Graphics

With big bang system delivery, expanding design space and lack of resources, it's no wonder Design Verification is a stressful part of development. Practices from Agile software development can smooth many of the stressful and unpredictable situations faced in SoC hardware development. By prioritizing quality, collaboration and key customer features, agile development practices can help SoC build a predictable and sustainable development methodology. This panel of pioneers will demystify Agile hardware development by answering your questions and providing insights into why Agile is not exclusively a software phenomenon, but one that SoC teams should start using.

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Industry Standards (UVM, UPF, Portable Stimulus & SystemVerilog), and FPGA Trends Sessions

Industry Standards and FPGA Verification Trends

Video | Slides

Harry Foster - Mentor Graphics

This DAC Verification Academy theater session consist of two parts. First, adoption trends for various Accellera and IEEE standards will be presented—as well as an overview discussion of the advanced verification technologies that they enable. Next, this session shifts its focus specifically to FPGA verification trends as identified by the recent 2014 Wilson Research Group Functional Verification Study.

Off and Running with UVM

Video | Slides

Tom Fitzpatrick - Mentor Graphics

Whether you've spent years working with UVM or are a newcomer, this session will show you how to be more effective in deploying UVM in your verification flow. After a brief update on UVM standardization, we'll introduce Mentor's new UVM Framework, which provides a proven infrastructure for establishing a reusable company-wide verification library, and supports simulation and emulation, as well as testplan and coverage tracking. We'll close with an overview of new UVM capabilities in Questa so you can see how everything comes together.

UVM Debug? Beyond Logfiles

Video | Slides

Rich Edelman - Mentor Graphics

Today UVM testbenches are widely used to generate stimulus variants, and collect functional coverage, and today's UVM testbenches are complex object oriented software programs in their own right. And yet, debugging these testbenches is sometimes relegated to manually printing large quantities of information to the transcript file and trawling through it for snippets and symptoms. Come and hear about tips and tricks to move beyond logfiles, towards better UVM Debug.

EZ Design and Verification of ARM® AMBA® Based Designs

Video | Slides

William Orme - ARM® Ltd. & Jason Polychronopoulos - Mentor Graphics

Today's market calls for the creation of highly complex designs within short schedules, leading to numerous challenges in both design and verification. This joint presentation from William Orme, ARM® and Jason Polychronopoulos, Mentor Graphics shows how these challenges have been overcome by combining the latest design and verification IP for a complete verification flow from system level modelling, through simulation, emulation and FPGA prototyping. Expect to learn about the latest easy-to-use VIP from Mentor for ARM® AMBA® protocols and the latest ARM® IP and tools, along with how they can be used together for a complete design and verification solution.

Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF

Video | Slides

Ellie Burns - Mentor Graphics

IEEE 1801 UPF enables specification of the "power intent" of a design so that it's functionality can be verified along with design functionality early in the design process. A new methodology called Successive Refinement which articulates power intent into constraints, configuration, and implementation that is added incrementally, was conceived and refined within IEEE 1801-UPF and is now ready for broader adoption in the industry. This presentation will cover how to use the UPF Successive Refinement methodology in detail, how it can accelerate design and verification with a re-usable IP to System flow, and simplify the debugging of complex power management architectures. We will illustrate these advantages by applying the methodology to an ARM® IP-based system design.

Boosting Test-Creation Productivity with Portable Stimulus

Video | Slides

Tom Fitzpatrick - Mentor Graphics

Today's designs must be verified at block and system level, using simulation, emulation, and silicon engines. This session shows how a portable stimulus specification raises the abstraction level, enables automated test creation, and maximizes reuse. Portable stimulus boosts test-creation productivity 10-100x, and enables test reuse across simulation, emulation, and post-silicon engines.

Cadence and Mentor Kickoff Collaboration for open Debug Data API

Video | Slides

Adam Sherer - Cadence & Ellie Burns - Mentor Graphics

It has been 20 years since the approval of the VCD syntax in IEEE Verilog 1364-1995 that enabled industry-wide interoperability for change/debug data. At that time, it suited its purpose well offering an open and efficient way for data producers such as simulators, emulators and prototype boards, to exchange data with consumers such as testers, debuggers, power analysis tools, that need stimulus to drive them or perform analysis and debug on the results. With the size of designs growing from one million to one billion gates, however, this ASCII file based approach is struggling to handle the data exchange requirements of today. This session will discuss the kickoff of the collaboration between Mentor and Cadence to address this industry challenge with an open and efficient Debug Data API (DDA).

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Formal Verification Sessions

Trends in Formal Verification: Not Just for Experts Anymore!

Video | Slides

Harry Foster - Mentor Graphics

This session opens up a day at the DAC Verification Academy theater dedicated exclusively to formal techniques. In this session, industry trends will be presented with an emphasis on formal verification technology adoption and solutions.

Starting Formal Right from Formal Test Planning

Video | Slides

Jin Zhang - Oski Technology

Verification planning is key to the success of any verification tasks and this is especially true for formal verification. Formal technology, while it can be very powerful in proving complete functional correctness of designs, is not suited for all design types. This session discusses the 3 stages of Formal Test Planning – IDENTIFYING the right design blocks for formal verification; ESTIMATING the formal verification effort using key metrics; and PLANNING the actual formal verification tasks on the chosen designs. Through real life case studies, readers(audience) will learn how to start formal verification right from Formal Test Planning.

How to Keep UPF from Ruining Your CDC Analysis

Video | Slides

Kurt Takara - Mentor Graphics

The addition of power control logic via a Unified Power Format (UPF) file can introduce new multi-clock issues into your designs if you're not careful. Incorrect power control logic insertion is but one of many problems that can ruin your whole CDC analysis. In this presentation we will discuss the effects of advanced low power design on CDC by the addition of isolation cells, retention cells, level shifters, and dynamic voltage scaling.

Formal Model Checking: From Oblivion to a Pillar of Success

Video | Slides

Ram Narayan - Oracle

This session will describe how formal methods went from being used opportunistically to a central place in the verification methodology of the RAPID SoC to help the Oracle team achieve its verification goals of finishing on schedule and achieving first pass silicon success.

Instant Formal Expert - UPDATED

Video

Jeremy Levitt - Mentor Graphics

What are formal property checking engines and how do they work? Why are they incredibly powerful for some properties, but not so good for others? What's the state of the art and what's coming in the near future? In this talk, we'll review the fundamentals as well as the recent breakthroughs that are driving advances in performance and capacity. Join us to instantly become a formal expert!

How Secure is Your System?

Video | Slides

Joe Hupcey III - Mentor Graphics

Whether it's a private encryption key for mobile payments, a milaero communications system, or a patient's therapeutic parameters; verification of hardware access to secure storage elements is a challenging and critical task. For safety critical systems in addition to risks from external hacking, designers must ensure unexpected side-effects or bugs cannot inadvertently corrupt critical data. This session will discuss how the Secure Check app can be the foundation of your "root of trust".

New Coverage Closure Techniques

Video | Slides

Mark Eslinger - Mentor Graphics

Achieving coverage closure goals on time and under budget is one of the most visible and challenging assignments in functional verification today. Attend this session to hear how a mix of formal apps and methodologies including, recording and tracking coverage with the Unified Coverage Database (UCDB), as per the Accellera Unified Coverage Interoperability Standard (UCIS).

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