Industry Standards and FPGA Verification Trends
Harry Foster - Mentor Graphics
This DAC Verification Academy theater session consist of two parts. First, adoption trends for various Accellera and IEEE standards will be presented—as well as an overview discussion of the advanced verification technologies that they enable. Next, this session shifts its focus specifically to FPGA verification trends as identified by the recent 2014 Wilson Research Group Functional Verification Study.
Off and Running with UVM
Tom Fitzpatrick - Mentor Graphics
Whether you've spent years working with UVM or are a newcomer, this session will show you how to be more effective in deploying UVM in your verification flow. After a brief update on UVM standardization, we'll introduce Mentor's new UVM Framework, which provides a proven infrastructure for establishing a reusable company-wide verification library, and supports simulation and emulation, as well as testplan and coverage tracking. We'll close with an overview of new UVM capabilities in Questa so you can see how everything comes together.
UVM Debug? Beyond Logfiles
Rich Edelman - Mentor Graphics
Today UVM testbenches are widely used to generate stimulus variants, and collect functional coverage, and today's UVM testbenches are complex object oriented software programs in their own right. And yet, debugging these testbenches is sometimes relegated to manually printing large quantities of information to the transcript file and trawling through it for snippets and symptoms. Come and hear about tips and tricks to move beyond logfiles, towards better UVM Debug.
EZ Design and Verification of ARM® AMBA® Based Designs
William Orme - ARM® Ltd. & Jason Polychronopoulos - Mentor Graphics
Today's market calls for the creation of highly complex designs within short schedules, leading to numerous challenges in both design and verification. This joint presentation from William Orme, ARM® and Jason Polychronopoulos, Mentor Graphics shows how these challenges have been overcome by combining the latest design and verification IP for a complete verification flow from system level modelling, through simulation, emulation and FPGA prototyping. Expect to learn about the latest easy-to-use VIP from Mentor for ARM® AMBA® protocols and the latest ARM® IP and tools, along with how they can be used together for a complete design and verification solution.
Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF
Ellie Burns - Mentor Graphics
IEEE 1801 UPF enables specification of the "power intent" of a design so that it's functionality can be verified along with design functionality early in the design process. A new methodology called Successive Refinement which articulates power intent into constraints, configuration, and implementation that is added incrementally, was conceived and refined within IEEE 1801-UPF and is now ready for broader adoption in the industry. This presentation will cover how to use the UPF Successive Refinement methodology in detail, how it can accelerate design and verification with a re-usable IP to System flow, and simplify the debugging of complex power management architectures. We will illustrate these advantages by applying the methodology to an ARM® IP-based system design.
Boosting Test-Creation Productivity with Portable Stimulus
Tom Fitzpatrick - Mentor Graphics
Today's designs must be verified at block and system level, using simulation, emulation, and silicon engines. This session shows how a portable stimulus specification raises the abstraction level, enables automated test creation, and maximizes reuse. Portable stimulus boosts test-creation productivity 10-100x, and enables test reuse across simulation, emulation, and post-silicon engines.
Cadence and Mentor Kickoff Collaboration for open Debug Data API
Adam Sherer - Cadence & Ellie Burns - Mentor Graphics
It has been 20 years since the approval of the VCD syntax in IEEE Verilog 1364-1995 that enabled industry-wide interoperability for change/debug data. At that time, it suited its purpose well offering an open and efficient way for data producers such as simulators, emulators and prototype boards, to exchange data with consumers such as testers, debuggers, power analysis tools, that need stimulus to drive them or perform analysis and debug on the results. With the size of designs growing from one million to one billion gates, however, this ASCII file based approach is struggling to handle the data exchange requirements of today. This session will discuss the kickoff of the collaboration between Mentor and Cadence to address this industry challenge with an open and efficient Debug Data API (DDA).
