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Streamlining Requirements Traceability using Questa Verification IQ Testplan Author
Webinar - May 28, 2025 by Nishtha NLN
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) to deliver a powerful, collaborative traceability solution that transforms your verification workflow.
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Solving the Semiconductor Verification Crisis: From Problem to Productivity
Webinar - May 21, 2025 by Harry Foster
In this webinar, you will learn more about the challenges that are currently being faced by the digital design and verification industry and the steps you can take to mitigate some of these challenges.
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Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
Resource (Slides Download) - May 07, 2025 by Ann Keffer
This webinar will offer valuable insights into leveraging functional fault grading for robust and reliable system designs.
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Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
Webinar - May 07, 2025 by Ann Keffer
In this webinar, we will explore how functional fault grading enhances defect coverage. Attendees will learn the key advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.
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Our Journey in Deploying Formal Register Checks with Questa Check Register
Resource (Slides Download) - May 01, 2025 by Thomas Thatcher - Rambus
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Our Journey in Deploying Formal Register Checks with Questa Check Register
Resource (Recording) - May 01, 2025 by Thomas Thatcher - Rambus
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Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification
Resource (Recording) - May 01, 2025 by Mitchell Poplingher
In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.
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Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification
Resource (Slides Download) - May 01, 2025 by Mitchell Poplingher
In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.
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Tackling Formal Verification of Large Designs using a Modular Approach
Resource (Slides Download) - May 01, 2025 by Ratish Punnoose - Sandia National Laboratories
Performing formal verification of an SoC type design in one go is limited by the tractability of the formal checks as well as by the complexity of writing an assertion that captures the full behavior. We describe approaches to perform verification in a modular way while maintaining assume-guarantee reasoning between the verification units.
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Tackling Formal Verification of Large Designs using a Modular Approach
Resource (Recording) - May 01, 2025 by Ratish Punnoose - Sandia National Laboratories
Performing formal verification of an SoC type design in one go is limited by the tractability of the formal checks as well as by the complexity of writing an assertion that captures the full behavior. We describe approaches to perform verification in a modular way while maintaining assume-guarantee reasoning between the verification units.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Slides Download) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Recording) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.
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osmosis 2025 - Ask the Experts Panel
Resource (Recording) - May 01, 2025 by Chris Giles
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osmosis 2025
Conference - May 01, 2025 by Nicolae Tusinschi
The annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.
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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity
Webinar - Apr 30, 2025 by Kevin Ham
This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.
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Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
Resource (Slides Download) - Apr 30, 2025 by Kevin Ham
This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity.
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Securing your FPGA Design from RTL through to the Bitstream
Webinar - Apr 23, 2025 by Keerthi Devraj
This session will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy. In addition, we will introduce Bitwise (powered by Red Balloon Security) as a point-and-click assurance tool that delivers rapid security analysis and hardening of FPGA bitstreams.
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Securing your FPGA Design from RTL through to the Bitstream
Resource (Slides Download) - Apr 23, 2025 by Keerthi Devraj
This session will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy.
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Closing the Gap in Software Skills for Verification Engineers
Resource (Verification Horizons Blog) - Apr 17, 2025 by Dave Rich
I’m excited to announce next month’s U2U (User-to-User) meeting , followed by a crucial technical training session that no hardware verification engineer should miss.
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Faster Debug Using QuestaSim Interactive Coverage Analysis
Resource (Slides Download) - Apr 16, 2025 by Justin Royse
In this webinar, you will learn how interactive coverage analysis brings another dimension to RTL and SV/UMV debugging which can lead to significant productivity boost and faster design and testbench bring up.
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Faster Debug Using QuestaSim Interactive Coverage Analysis
Webinar - Apr 16, 2025 by Justin Royse
This session we will explore the power of debugging code and functional coverage while simulation is still running. Learn how interactive coverage analysis brings another dimension to RTL and SV/UMV debugging which can lead to significant productivity boost and faster design and testbench bring up.
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Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Webinar - Apr 03, 2025 by Mark Carey
This session will explore the powerful Smart Debug features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution. Leveraging advanced machine learning technology, these features enable you to accelerate root cause analysis and reduce debug turnaround time.
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Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Resource (Slides Download) - Apr 03, 2025 by Mark Carey
This session will explore the powerful Smart Debug features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution.
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PCIe Gen7 Verification with Siemens Avery Verification IP
Webinar - Mar 26, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
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PCIe Gen7 Verification with Siemens Avery Verification IP
Resource (Slides Download) - Mar 26, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.