Verification Academy at DAC 2018 | Verification Academy

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Monday, June 25th

Portable Stimulus: A New Hope

10:00 AM | Tom Fitzpatrick - Mentor, A Siemens Business

The new Portable Stimulus Standard from Accellera provides the next leap in verification productivity for SoC verification. From a single abstract specification of test intent and coverage, tools can automate the generation of multiple target-specific test implementations for different platforms throughout the verification process, from virtual prototypes to RTL simulation, emulation, FPGA prototypes and post-silicon, freeing the verification team from the tedious and error-prone process of trying to re-implement tests in different languages. This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology. We will also show how Questa inFact, Mentor’s portable stimulus solution, will allow you to witness the power of this fully operational standard.

UVM 1800.2 & The New and Improved UVM Cookbook

11:00 AM | Tom Fitzpatrick - Mentor, A Siemens Business

With the approval of the IEEE 1800.2 UVM Standard, and the new Reference Implementation from Accellera, UVM has reached its peak as the dominant verification methodology available. This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard. To accompany this release, we have updated the online UVM Cookbook both to take advantage of some of the new features in UVM and also to guide you in creating testbenches that can be reused in all available engines, including emulation. We will also see how the UVM Framework will automatically build your environment according to these new guidelines, letting you get a UVM environment up and running in just a few hours. Even if you’ve been using UVM for years, we’ll show you how you can be even more efficient and portable in creating your UVM environment.

A Designer Life with HLS – Faster Computer Vision/Neural Networks

12:00 PM | Corneliu Zaharia & Szabolcs Fülöp - FotoNation

As a company with a history of innovation and experience in computational imaging algorithms, FotoNation is always looking for ways to speed up their development processes. This presentation will discuss two aspects of their experience going from RTL to HLS. The first topic is using HLS for algorithms such as Face Detection that they know well with RTL for comparison. The second is to use HLS to develop new Neural Network accelerators and how HLS could help them get from algorithm to critical FPGA demonstrators in a time which would not be possible with a traditional RTL flow.

Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless visibility at SOC level

1:00 PM | Rohit Kumar Sinha - Intel India

CDC Analysis at SOC level involves huge challenges in terms of capacity, quality of results, and ease of debug, dependencies and ownership of IPs. The SOC’s belong to the flagship products and typically the biggest and complex. In this project, there were around 78 IPs (external & internal) and 5 subsystems. IPs get sourced from both internal as well external world and they get integrated at the SOC level later in the design cycle. In the hierarchical approach, CDC analysis is done in a bottom-up approach wherein CDC analysis for the IP level is done first and its abstract model (HDM model) is created based on SOC/Subsystem level parameters and configuration. HDM is third generation abstraction flow with enhanced capabilities for debug as SOC level and improved quality of results. HDM models provide a seamless visibility of internal logic when consumed at the SOC level. Improved quality of results was possible as HDM’s are instance based and encapsulated parameter values to effectively check at SOC level. Seamless Reconvergence analysis across multiple hierarchies was possible with HDM. With enhanced HDM flow debug was easy and quality of results were pristine and CDC Analysis at SOC level was fool proof.

Demonstrating Functional Safety Compliance in Automotive IC Design

2:00 PM | Srikanth Rengarajan - Austemper Design Systems

Functional Safety compliance has taken center stage in the automotive industry with rigorous, semiconductor-level processes and failure targets embodied on the ISO 26262 standard. Certifying such compliance to the relevant ASIL tier, particularly in the face of growing design complexity and closer assessment scrutiny, calls for new paradigms and thinking. Traditionally, practitioners were able to rely on legacy architectures and use-models combined with targeted verification for selected logic units using customer-specific methodologies. For the highest safety levels, logic or component replication offered a way out. The enhanced scrutiny for level3+ autonomous driving made possible by new IC architectures makes the former approach unattractive while the economics of the hardware costs make replication unviable. From a standards perspective, the preference for Fault simulation is made clear but safety engineers face a few obstacles to widespread adoption of Fault sims as the de-facto methodology. In this presentation, we will review some of the hurdles holding the industry back from conducting exhaustive fault campaigns and some innovative approaches to solving them. Also included is a review of acceleration strategies and best practices to enable them.

2018 Wilson Research Group ASIC/IC Functional Verification Trends

3:00 PM | Harry Foster - Mentor, A Siemens Business

Want to learn more about the latest industry trends in ASIC/IC functional verification? Following the success of the four previously critically acclaimed Wilson Research Group Functional Verification Studies, the new 2018 industry-wide study was just completed. And for the first time the latest ASIC/IC functional verification industry trends will be revealed at this year’s DAC 2018 Verification Academy booth.

Portable Stimulus versus UVM: What's the Difference?

4:00 PM | John Aynsley - Doulos

We compare the Accellera Portable Test and Stimulus Standard (PSS) with the Universal Verification Methodology (UVM), and ask exactly what the difference is between the two when it comes to generating stimulus for hardware verification and SoC verification.

It’s Been 24 Hours – Should I Kill My Formal Run?

5:00 PM | Jeremy Levitt - Mentor, A Siemens Business

This time yesterday you kicked off a formal analysis – and it’s still running! Is it making any progress, or should you kill it now and start over? In this talk we will show how to make an informed decision using “engine health” monitoring, a snapshot of the active logic being used by the analysis, and making an honest appraisal of the assumptions you applied at the beginning of the run. Plus: we’ll show how a secure mobile app can be employed to keep track of progress of formal runs when you are away from your workstation.

Be careful that your initial assumptions are not too broad

Confirm the relevance of the DUT logic being included in the analysis

Leverage “engine health” indicators

Tuesday, June 26th

Portable Stimulus from IP to SoC - Achieve More Verification

10:00 AM | Matthew Ballance - Mentor, A Siemens Business

With so much of the buzz about the emerging Accellera Portable Stimulus Standard centered around applications in the system level space, it might seem that this is the sole application for the technology. However, users have long been applying portable stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity. This presentation will show how Mentor’s inFact portable stimulus tool is applied across the verification spectrum and the spectrum of verification engines to achieve more verification with the same resources.

Building An Integrated Verification Flow

11:00 AM | Neil Johnson - XtremeEDA

While a lot of information is produced to introduce and support individual verification techniques, methods for applying a variety of verification techniques in a complementary way are harder to come by. In this session, we’ll discuss the factors and decisions that go into building an effective verification flow including what techniques to use and how they can be used together.

Micgelo: A Proven Flow to Reduce Clock Tree Power with Fast TAT

12:00 PM | Jianfeng Liu - Samsung

Low power design is critical for chip and IP designs in mobile and IOT age. A significant portion of dynamic power is consumed by Clock Gating (CG) cells. The traditional flow of optimizing instantiated CG cells is to capture data from implementation team to RTL team, which is late in RTL development cycle. To provide better Turn Around Time (TAT), we are proposed a methodology - Micgelo (Metric Driven Clock Gate Cell Optimization), to audit the quality of CG and flop’s enable at early RTL development cycle. Hence, RTL team need not to be dependent on implementation team for the data to be reviewed. It is further very helpful to implementation team as well because it resolves the clock-network specific challenges upfront. The Micgelo Flow comprises of several clock gating metrics: Clock Gating Efficiency, Relative Integrated Clock Gate Efficiency, Absolute Integrated Clock Gate Efficiency and Weighted Integrated Clock Gate impact on clock Cycle reduction. The Micgelo methodology has been validated over several IPs/blocks from RTL design to Gate implementation, and significant improvement on power and TAT was observed by the proposed flow.

2018 Wilson Research Group FPGA Functional Verification Trends

1:00 PM | Harry Foster - Mentor, A Siemens Business

What to earn more about the latest industry trends in FPGA functional verification? Following the success of the four previously critically acclaimed Wilson Research Group Functional Verification Studies, the new 2018 industry-wide study was just completed. And for the first time the latest FPAG functional verification industry trends will be revealed at this year’s DAC 2018 Verification Academy booth.

Power Aware Simplifies Parametric PA-SIM Regression

2:00 PM | Ashish Amonkar - Cypress Semiconductor

Power Aware simulations play an important role in the System resources block verification. However parametric UPF brings about its own challenges with respect to simulating it in a regression environment. So there is a need to load a dynamically generated UPF based on varying parameter sets. Questa Power Aware helps simplify this effort with loading the UPF in the .tcl format. The parameters like number of watchdogs are set in a configuration file which is used to generate a dynamic test tree which contains a tcl file that loads the UPF. This tcl file is then passed into the optimization stage of the Questa Power Aware tool to load the UPF. UVM tests can now be run with these dynamic test trees to get power aware simulations to cover the wide parameter space.

AMS Verification Methodology for GPUs in AI and Deep Learning Applications

3:00 PM | Sathish Balasubramanian - Mentor, A Siemens Business

Artificial Intelligence and Deep learning based applications are the main drivers behind the current exponential increase in demand for computational power. This demand is predominantly being addressed now by GPUs instead of traditional CPUs. GPUs are high-performance, high-throughput chips which require I/O bandwidth of the order of Gbps and high-bandwidth memory interfaces. This talk will provide an overview of the AI and deep learning applications using GPUs, the added complexities on AMS verification and the methodology used to address these verification challenges in efficient and predictable ways.

Superbugs: Leveraging Formal Verification to Combat Simulation Resistant Bugs

4:00 PM | Vigyan Singhal - Oski Technology

“Superbugs” can survive because of simulation’s inability to test all possible functional scenarios. Simulation coverage closure is difficult and coverage models represent a limited view of the design’s behavior. Critical bugs may go undetected, leaving your design at risk of failure. Oski Formal methodology with formal coverage closure and abstraction models can be applied to various applications to ensure simulation resistant bugs are vanquished.

Using Automation to Close the Loop Between Functional Requirements and their Verification

5:00 PM | Brian Craw - Cypress Semiconductor

With Coverage Intent, and Test we now have the means to directly connect functional coverage and test status to the requirements they meet. Work items can be linked together in custom relationships. This session will defined a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation. Lastly will discuss how to import the report, parse the coverage item and test names, and back-annotate the Coverage Intent and Test work items with their corresponding coverage percentages and status.

Wednesday, June 27th

Veloce Emulation Platform Brings Unique Solutions to Automotive Market

10:00 AM | Vijay Chobisa - Mentor, A Siemens Business

Major trends such as ADAS/Autonomous driving, Connectivity and Advanced security are on the verge of revolutionizing the way automobiles are used. These trends bring significant implications for the design and verification of increasingly complex electronic systems. For instance, ADAS/autonomous driving demands much higher levels of HW/SW integration and complexity, and a huge quantity of sensor data that needs to be processed. And of course many functions are safety critical as defined within the context of ISO 26262. All of this puts massive strain on current verification techniques, and requires the emergence of new equally innovative verification technologies to answer to all aspects of automotive electronics design. Join us for this session as we explore how the Veloce Emulation platform is positioned to deliver optimal verification solutions for the automotive market.

Virtual Method Upcasting & Downcasting And Their Use In UVM

11:00 AM | Cliff Cummings - Sunburst Design

The UVM class library is mostly composed of virtual classes with virtual methods. When overriding a virtual method, SystemVerilog, requires the use of the exact same method prototype, which requires verification engineers to do upcasting and downcasting. This presentation shows how upcasting and downcasting work and how they are frequently used in UVM testbench environments.

The Next Big Thing in Design Driving the Next Big Thing in Verification

1:00 PM | Harry Foster - Mentor, A Siemens Business

Our industry has experienced remarkable breakthroughs in computing, networking, and communication technology in recent years. Yet, it is the convergence of these technologies that is driving the next big thing in innovation related to IoT and autonomous systems. And it is also driving the need for new approaches to verify today’s complex systems. In this Verification Academy session, Harry Foster shares a holistic view of the next big wave in verification.

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

2:00 PM | Kurt Takara - Mentor, A Siemens Business

There you are, satisfied that all of your tape out criteria were met: at the RTL level, every form of “coverage” you could think of was applied, and 100% coverage scores were achieved across-the-board. Similarly, your RTL clock domain crossing (CDC) verification was clean. At the gate level, all the gate-level simulations (GLS) passed with flying colors, and weeks of static timing analysis (STA) came to a successful close. Yet here you are in the lab, hovering over samples that keep rebooting at seemingly random intervals since you first powered them up. What can be done in this situation? In this presentation we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

Using HLS to Accelerate Computer Vision for Autonomous Drive

3:00 PM | Ellie Burns - Mentor, A Siemens Business

The algorithms to teach a computer to “see, understand and make decisions” for ADAS and Autonomous Drive systems require a significant amount of parallel compute performance executing at the lowest possible power. This session will introduce of why HLS (High-level Synthesis) is such a good fit for computer vision and deep learning and how it can be used adapt rapidly changing algorithms and/or trained neural networks to low-power, high performance custom hardware accelerators.

Validating Your SoC is True to Requirements

4:00 PM | Stephen Bailey - Mentor, A Siemens Business

Do you verify your designs or do you validate them? Trick question! While related, validation is different from verification, not a synonym or replacement for it. Validation certifies the SoC is true to the marketing requirements. That is, if marketing did their job right, then validation ensures the SoC will be a successful product. As challenging as verification is, validation is even more so. Let’s explore how to validate all dimensions of functionality, performance, power and potentially for systems-on-chip.

Data Mining for SoC Level Performance

5:00 PM | Mark Olen - Mentor, A Siemens Business

You've written 1000's of constraints, assembled several testbenches, written coverage models, and run 100's of simulations to verify your IP blocks. You've achieved nearly 99% code coverage and even 95% of your functional coverage. You've even run SoC level emulations runs, and found (and repaired) several hardware software integration problems. But when you get to the lab, you still see intermittent design performance problems. This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

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