Veloce Emulation Platform Brings Unique Solutions to Automotive Market
10:00 AM | Vijay Chobisa - Mentor, A Siemens Business
Major trends such as ADAS/Autonomous driving, Connectivity and Advanced security are on the verge of revolutionizing the way automobiles are used. These trends bring significant implications for the design and verification of increasingly complex electronic systems. For instance, ADAS/autonomous driving demands much higher levels of HW/SW integration and complexity, and a huge quantity of sensor data that needs to be processed. And of course many functions are safety critical as defined within the context of ISO 26262. All of this puts massive strain on current verification techniques, and requires the emergence of new equally innovative verification technologies to answer to all aspects of automotive electronics design. Join us for this session as we explore how the Veloce Emulation platform is positioned to deliver optimal verification solutions for the automotive market.
Virtual Method Upcasting & Downcasting And Their Use In UVM
11:00 AM | Cliff Cummings - Sunburst Design
The UVM class library is mostly composed of virtual classes with virtual methods. When overriding a virtual method, SystemVerilog, requires the use of the exact same method prototype, which requires verification engineers to do upcasting and downcasting. This presentation shows how upcasting and downcasting work and how they are frequently used in UVM testbench environments.
The Next Big Thing in Design Driving the Next Big Thing in Verification
1:00 PM | Harry Foster - Mentor, A Siemens Business
Our industry has experienced remarkable breakthroughs in computing, networking, and communication technology in recent years. Yet, it is the convergence of these technologies that is driving the next big thing in innovation related to IoT and autonomous systems. And it is also driving the need for new approaches to verify today’s complex systems. In this Verification Academy session, Harry Foster shares a holistic view of the next big wave in verification.
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
2:00 PM | Kurt Takara - Mentor, A Siemens Business
There you are, satisfied that all of your tape out criteria were met: at the RTL level, every form of “coverage” you could think of was applied, and 100% coverage scores were achieved across-the-board. Similarly, your RTL clock domain crossing (CDC) verification was clean. At the gate level, all the gate-level simulations (GLS) passed with flying colors, and weeks of static timing analysis (STA) came to a successful close. Yet here you are in the lab, hovering over samples that keep rebooting at seemingly random intervals since you first powered them up. What can be done in this situation? In this presentation we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)
Using HLS to Accelerate Computer Vision for Autonomous Drive
3:00 PM | Ellie Burns - Mentor, A Siemens Business
The algorithms to teach a computer to “see, understand and make decisions” for ADAS and Autonomous Drive systems require a significant amount of parallel compute performance executing at the lowest possible power. This session will introduce of why HLS (High-level Synthesis) is such a good fit for computer vision and deep learning and how it can be used adapt rapidly changing algorithms and/or trained neural networks to low-power, high performance custom hardware accelerators.
Validating Your SoC is True to Requirements
4:00 PM | Stephen Bailey - Mentor, A Siemens Business
Do you verify your designs or do you validate them? Trick question! While related, validation is different from verification, not a synonym or replacement for it. Validation certifies the SoC is true to the marketing requirements. That is, if marketing did their job right, then validation ensures the SoC will be a successful product. As challenging as verification is, validation is even more so. Let’s explore how to validate all dimensions of functionality, performance, power and potentially for systems-on-chip.
Data Mining for SoC Level Performance
5:00 PM | Mark Olen - Mentor, A Siemens Business
You've written 1000's of constraints, assembled several testbenches, written coverage models, and run 100's of simulations to verify your IP blocks. You've achieved nearly 99% code coverage and even 95% of your functional coverage. You've even run SoC level emulations runs, and found (and repaired) several hardware software integration problems. But when you get to the lab, you still see intermittent design performance problems. This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.
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