UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). UVM Connect allows you to reuse your SystemC architectural models as reference models in UVM verification and/or reuse SystemVerilog UVM agents to verify models in SystemC. It also effectively expands your VIP portfolio since you now have access to VIP in both languages. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.
For UVM connect resources, downloads and documentation please refer to the UVM Connect overview page.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses, then the recommended prerequisites; Basic UVM, Advanced UVM.