UVM Basics
UVM Basics will raise a user's level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.
-
Sessions
-
Introduction to UVM
This session gives an overview of UVM, the motivation and benefits, and technical highlights. -
UVM "Hello World"
This session walks through a short, simple example to get you started with UVM. -
Connecting Env to DUT
This session explains how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database. -
Connecting Components
This session explains the phases of a UVM component, focusing on how to use the build and connect phases. -
Introducing Transactions
This session explains how to use transactions to communication between a sequencer and a driver in UVM. -
Sequences and Tests
This session explains how to create sequences of transactions, sequences of sequences, and how to start a sequence from a test. -
Monitors and Subscribers
This session explains how to create passive components such as monitors and subscribers, and how to connect them using analysis ports. -
Reporting
This session explains message reporting in UVM, and shows simple ways in which reporting can be customized.
-
-
Overview
The UVM (Universal Verification Methodology) Basics track is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming.
Requirements
- A working knowledge of VHDL or Verilog is recommended for the majority of this learning track
- Prior knowledge of SystemVerilog would be useful, but not required