Power Aware CDC Verification
In this track, you will learn the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.
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Sessions
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Power Aware CDC Introduction and Overview
This session introduces the design challenges created by low power designs and the implications that these designs have on CDC verification. -
Understanding Low Power Impact on CDC Logic
This session describes the impact of low power design techniques on design and CDC logic and also explains dynamic voltage and frequency scaling (DVFS) and its effect on CDC design and verification. -
Describing Low Power Logic with UPF
This session describes the clock-domain crossing requirements for low power designs and explains the CDC issues introduced by power control logic. -
Integrating Power Aware CDC into a Design Flow
This session describes a low power verification methodology and how the Questa Power Aware CDC solution may be integrated into your design flow. -
Questa CDC Power Aware
This session demonstrates the Questa CDC Power Aware solution for verifying low power designs including clock domain crossing (CDC) and voltage domain crossing (VDC) paths.
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Overview
Reducing power consumption is essential to mobile and handheld application chips where reduced power contributes to longer battery life while minimally impacting performance. As more designs incorporate low power strategies, CDC errors are being found in the low power structures. Since low power logic is implemented late in the design cycle, these low power CDC issues are being missed by traditional CDC techniques.
CDC verification has become a mainstreamed tape out criteria. Design teams know that CDC verification is required to avoid metastability issues that result in reliability and functional problems in silicon. However, the low power design techniques are creating new CDC challenges that are not always addressed by traditional CDC methodologies and solutions. For example, leading-edge designs are now employing dynamic voltage and frequency scaling (DVFS) techniques that change the synchronous relationships between clocks. Now, designers must verify voltage domain crossing (VDC) paths in addition to the normal CDC paths.
The additional challenge is that the power logic is not represented in the RTL design, but the power information is described in the unified power format (UPF) files. In the design flow, the power logic is not added until the implementation phase, but designers cannot wait until the implementation phase to complete the CDC analysis. Completing the CDC verification on the low power logic at the RTL design phase is critical to reducing the costs of identifying and fixing low power CDC issues.
In the process of helping project teams deploy power aware clock-domain crossing verification, we have discovered new CDC artifacts and developed new CDC techniques. This Verification Academy course describes the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.
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Forum Discussion - Power Aware
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