The Basic OVM (Open Verification Methodology) course module consists of approximately 2.5 hours of content, and is divided into eight sessions. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained-random verification or object-oriented programming.
Our goal for releasing the Basic OVM course is to raise your skill level to the point where you have sufficient confidence in your own technical understanding. Thus, giving you the confidence required to start the process of adopting advanced functional verification techniques.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses.
