Released on March 31st, 2021
Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them. First, each requires a driver and receiver supply specification for input and output; otherwise, they may be wrongly driven by the primary supplies of the IO’s domain or by anonymous supplies that may cause unwanted corruption—or prevent corruption when needed. Next, attributing these driver or receiver supplies is not straightforward; there could potentially be various types of ‘design top’s: non-power-domain hierarchical RTL instance tops, multi-rail macro tops, and hierarchical RTL instance power domain (PD) tops. The IOs could be also input, output, or bidirectional inout types. Another complicating issue is that UPF 3.0 and 3.1 provide contradictory resolutions for attributing such IOs with the driver supply, receiver supply, domain’s primary supply, and/or a separate anonymous supply. Since design verification by simulation requirements extends at least through post synthesis gate-level designs, wrongly attributing the related supplies of ‘design top’ IOs could costs enormous burden on verification turn-around time. This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation. Our motivation is to create a complete low power verification solution for IOs that will be ultimately driven by off chip resources. The empirical studies in this paper enable us to comprehend the limitations of the current LRM and propose appropriate solutions that are universally applicable in RTL and post synthesis simulations.
