Ashish Amonkar

Ashish joined Cypress as a NCG from University of Colorado, Boulder with a M.S.E.E. Ashish transitioned from doing design and layout for Cypress SONOS Flash memory subsystems to doing mixed signal verification on PSoC3/5 chips using Questa ADMS. Ashish has successfully led the mixed signal verification effort on Cypress SONOS Flash Memory Subsystems across the various technology generations. With the advent of OVM and UVM methodologies Ashish started deploying these methodologies to make the System Resources test bench highly scalable and reusable across multiple variants of the design. Ashish has also successfully set up the Questa Power Aware Methodology on the System Resources block to accelerate the UPF verification closure across the various parameters in the design as well as complex power domain interactions. Ashish has vast experience of all phases of verification across digital, mixed signal and fast spice domains. He holds three patents in Flash memory design and systems as well.

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VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Ashish Amonkar

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