Adam Erickson

Adam Erickson is a Verification Methodologist at Siemens EDA, where he’s served as a principal developer of the OVM, UVM, and UVM Connect. Since earning his Masters in Engineering Sciences at Dartmouth College, Adam has collected 22 years experience in design, verification, and implementation of integrated circuits for companies large and small. He has committed the last 16 of those years developing EDA software and methodological solutions for increasing productivity and reuse in verification. He has authored articles for Verification Horizons and published several conference papers, including Best Paper on a cost-benefit analysis of UVM macros at DVCon 2010. When he’s not improving existing solutions or developing ideas for new ones, Adam can often be found teaching their virtues to others. Adam is currently the primary technical representative for Siemens EDA on the Accellera VIP-TSC, the committee responsible for UVM standardization.

Content by Adam Erickson

UVM Connect
UVMC May 23, 2022 Adam Erickson Track

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Adam Erickson

Content by Adam Erickson

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