Instantiate a uvm class in another class but not to run uvm_phases of class
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2
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34
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May 11, 2024
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Dynamic Array declaration
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1
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32
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May 10, 2024
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What happens when we assign a value to a net at the time of declaration?
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4
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29
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May 10, 2024
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About new tech learning
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0
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40
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May 10, 2024
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Start AHB sequence based on AXI sequence response
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0
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39
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May 10, 2024
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Does uvm_config_db pass by value or pass by reference?
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1
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42
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May 9, 2024
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Randomize dynamic array with unique values
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8
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1356
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May 9, 2024
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Set_type_override gives compile error
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3
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32
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May 8, 2024
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Confusion about threads
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2
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42
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May 8, 2024
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Help me to find the cross coverage percentage?
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4
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46
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May 8, 2024
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Adding Custom Lint Methodology
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1
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31
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May 8, 2024
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QuestaSim Performance Profiler
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1
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25
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May 8, 2024
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Initializing a Register File
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1
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28
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May 7, 2024
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SVA: Package for dynamic and range delays and repeats
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10
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22771
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May 7, 2024
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System verilog interview questions
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2
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70
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May 7, 2024
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Generate 200mz clock from 100mhz clock
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4
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47
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May 7, 2024
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Subordinated driver in agent
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4
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39
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May 7, 2024
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Discrepancy on legality of the consequent
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9
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105
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May 6, 2024
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System verilog interview question
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0
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53
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May 7, 2024
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Logical question
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9
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41
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May 6, 2024
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Why does the RAL read() update the mirrored AND desired register model values?
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3
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2972
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May 6, 2024
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Randomization of beats
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2
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42
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May 6, 2024
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How can we verify a memory whose address location is swapped
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19
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10742
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May 5, 2024
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Uvm_sequencer usage
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2
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54
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May 5, 2024
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Seq_item_port driver-sequencer - communication issue
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2
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45
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May 5, 2024
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Using goto repetition
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4
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311
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May 4, 2024
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UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation
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2
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169
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May 4, 2024
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While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object
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1
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41
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May 4, 2024
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Overriding UVM_NONE messages
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4
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44
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May 4, 2024
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Tackling a constraint in post_randomize()
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2
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59
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May 4, 2024
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