there is a dut statemachine which has four states referred as A B C ERROR . there is a condition on A called cond_1 when occures will make a transition from A to B. but that condition can occure at any point of time . and B to C it takes only one clock cycle.
and whenever there is an error in B it takes transition to ERROR state.and the error is generate by the RTL if hready is low for 8 clock cycles and along with if the condition of if we are not able to read or write to that slave.
there is a hole in coverage of B where we need to make all the below conditions to happen in single time.
cond_1 (which can occure at any point of time) and hready should be low and read/write should happen at the time when b transitions to C from B.
could you please clarify how we can control condition.