Logical question

SystemVerilog
1

i am new to functional coverage and system verilog can someone help me in a problem like in a 32 bit address suppose that any two bits are shorted how can we detect that further suppose 3 or 4 bits are shorted or even 15 bits are shorted how can we detect that and write a coverage giving such inputs that every shorted pins are covered, how to give inputs so that i am 100 percent satisfied, please explain in little detail as i am beginner

2

you can write at that address followed by read

3

not understood sabarish i already told you i am beginner so will need a little bit more explanation

5

Hi hk,
I meant you need to write coverage bins for all combinations starting with 2’b11, 3’b111 till 32’hFFFF_FFFF to achieve 100% coverage!!

6

can you just give me an example code i have just started and in that how will i detect how many bits are shorted and which are those bits, shorting is happening while transferring of data through protocol, it might be due to DUT logic also

7

sorry for asking soln but trying it for 15 days but unable to reach to any conclusion

8

and i guess if i write according to u i will get 32 factorial bins, i am looking for optimised soln too

10

This is a very big question to be completely answered in a forum.

Coverage is about recording that certain scenarios have happened in a test that has passed. Checking that the each scenario passes the test is a problem that can be separated from the coverage collection.

Let’s start with 2 bits shorted out of 2 bits, which is 32choose2=496 possible combinations. That could be implemented using a nested for loop.

for(int i=0;i<32;i++)
  for(int j=0;j<32;j++) begin
     if (i ==j) break; // skip same bit
     test_senario(i,j);
     cover_senario.sample(i,j);
end

To test that two bits are shorted, you need to write two different values to an address where one address bit is 0, and the other is a 1. The other address bits can be random.

  task test_senario(int, x,y);
    bit [31:0] addr1, addr2, data1, data2, xdata1, xdata2;
    addr1 = $urandom;
    addr2 = addr1;
    addr1[x] = 0;  addr1[y] = 1; 
    addr2[x] = 1;  addr2[y] = 0; 
    data1 = $urandom;
    data2 = $urandom;
    write_bus(addr1,data1);
    write_bus(addr2,data2);
    read_bus(data1,xdata1);
    read_bus(data2,xdata2);
    if (data1 != xdata1 || data2 != xdata2)
       $error("data does not match);
endtask

I don’t think you need to worry about three or more bits being shorted, this test should work for that as well.

You can use a coverage cross to sample the two bits

covergroup cg with function sample(int x,y);
  coverpoint x { bins select[] = {[0:1]}; }
  coverpoint y { bins select[] = {[0:1]}; }
  short: cross x,y {
   ignore_bins same = short with (x==y);
  }
endgroup
cg cover_scenario = new;
11

thank u sir for replying i will tru understanding solution if i am not able to understand will ask

12

thank u sir for replying i will try understanding solution if i am not able to understand will ask just one help can u give one example of one 4 bit address only how your coverage is detecting short