Generate 200mz clock from 100mhz clock

SystemVerilog
1

is there any efficient way to generate 200mhz clock from 100mhz clock.

always@(100_mhz_clk)
begin
200_mhz_clk=~200_mhz_clk;
#2.5 200_mhz_clk=~200_mhz_clk;

end
1 Like
2

Looks good!

3

but I dont waant to use 2.5 delay, how it can be done.

4

in order to generate a clk from another one, you need to use either clock_period value to make it T/4 or directly use 2.5ns which you did!

5

thank you Sabarish