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Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof.
According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars. Of all the stages that make up the entire design creation and verification flow, two account for more than 60% of the total cost. Hardware design verification consumes about $120M, and embedded software development and validation approximately twice as much, and the trend
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