Please login to view the entire Verification Horizons article.
Please register or login to view.
by Ben Cohen, Accellera Systems Initiative, VhdlCohen Publishing
Monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces. The basic concept involves using assertion statements along with functions, called from sequence match items, to collect the desired scoreboard information, to compare expected results to collected data, and to trigger covergroups. This concept is demonstrated using a UART transmitter as the DUT. Since the purpose of this model is to demonstrate the use of assertions to emulate verification logic, the driver for this DUT originates directly from a top level module. To demonstrate the difference between an assertion-verification solution versus a monitor/scoreboard-solution in classes, a monitor class was implemented.
CONCEPTS
Assertions imply an implementation with FSMs and logic. Assertions can be used to get to specific cycle points in the verification flow, and then from within sequence match items, user-defined functions can be called to affect changes to module or interface variables1. Those SV interface variables can be read from a class instance (e.g., the monitor class) connected to that interface; the monitor can then transfer the needed data and verification results to UVM analysis ports. The SV interface variables can also be used in covergroups to evaluate such things as range delays that were responded to by a DUT.2 The application of function calls from sequence match items
...
