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Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.
Mentor's System Design and Verification flow encapsulates a range of design and verification disciplines such as: embedded software; SystemC platform design and validation tools; and HDL simulation tools that can be used in various combinations using common
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