There have been multiple studies on IC/ASIC functional verification trends published over the years. However, there are no published studies specifically focused on Field-Programmable Gate Array (FPGA) verification trends. To address this dearth of information, this article highlights a few key FPGA findings from the 2018 Wilson Research Group Functional Verification Study. The findings from this study provide invaluable insight into the state of today’s FPGA market in terms of functional verification.
The Global Semiconductor Market
The global semiconductor market was valued at $444.70 billion in 2017, of which, $4.7 billion is accounted for by FPGAs. The FPGA market is expected to reach a value of $8.8 billion by 2027, growing at a compounded annual growth rate (CAGR) of 6.4% during this forecast period. The growth in this market is being driven by new and expanding end-user applications related to automotive, IoT, telecommunication, industrial, mil/aero, consumer, and emerging AI applications within the data center requiring acceleration.
Historically, FPGAs have offered two primary advantages over ASICs. First, due to their low NRE, FPGAs are generally more cost effective than IC/ASICs for low-volume production. Second, FPGAs’ rapid prototyping capabilities and flexibility can reduce the development schedule since a majority of the verification and validation cycles have traditionally been performed in the lab. More recently, FPGAs offer advantages related to performance for certain accelerated applications by exploiting hardware parallelism (e.g., AI Neural Networks).
Growing Design Complexity
The IC/ASIC market in the mid- to late-2000 timeframe underwent growing pains to address increased verification complexity. Similarly, we find today’s FPGA market is being forced to address growing verification complexity. With the increased capacity and capability of today’s complex FPGAs, and the emergence of high-performance SoC programmable FPGAs (e.g., Xilinx® Zynq®, Intel® Arria®, Cyclone®, and Stratix®, along with Microsemi® SmartFusion®), traditional lab-based approaches to FPGA verification and validation are becoming less effective. In this article, we quantify the ineffectiveness of today’s FPGA verification processes in terms of non-trivial bug escapes into production.
FPGA VERIFICATION EFFECTIVENESS
IC/ASIC projects have often used the metric “number of required spins before production” as a benchmark to assess a project’s verification effectiveness. Historically, about 30% of IC/ASIC projects are able to achieve first silicon success, and most successful designs are productized on the second silicon spin. Unfortunately, FPGA projects have no equivalent metric. As an alternative to IC/ASIC spins, our study asked the FPGA participants “how many non-trivial bugs escaped into production?” The results shown in Fig. 1 are somewhat disturbing. In 2018, only 16% of all FPGA projects were able to achieve no bug escapes into production, which is worse than IC/ASIC in terms of first silicon success, and for some market segments, the cost of field repair can be significant.
Figure 1 - Non-trivial FPGA bug escapes into production
For example, in the mil-aero market, once a cover has been removed on a system to upgrade the FPGA, the entire system needs to be revalidated.
FPGA VERIFICATION EFFORT
In this section, we discuss trends in terms of FPGA project time and resources.
Percentage of Project Time Spent in Verification
Fig. 2 shows the percentage of total FPGA project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product. On the other extreme, projects that spend a significant amount of time in verification often have a high percentage of newly developed design IP that must be verified.
Figure 2 - Percentage of FPGA project time spent in verification
Overall, we found an increase in average percentage of FPGA project time spent in verification during the period 2014 through 2018. This is an indication of growing design and verification complexity.
Mean Peak Number of Engineers
Perhaps one of the biggest challenges today is to control cost and engineering headcount, which means identifying FPGA design and verification solutions that increase productivity. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount. Fig. 3 shows the mean peak number of FPGA engineers working on a project.
While, on average, the demand for design engineers is growing at about a 4% CAGR (which is similar growth for IC/ASIC), the demand for verification engineers is growing at about a 10% CAGR. It is worth noting that during the period 2007 through 2014, the IC/ASIC market went through similar growth demands related to verification engineers to address growing verification complexity.
Figure 3 - Mean peak number of FPGA engineers on project
FPGA VERIFICATION ADOPTION TRENDS
To address growing verification complexity, we find that many FPGA projects have been forced to mature their verification processes. In this section, we present FPGA trends related to the adoption of various verification techniques, which are fairly standard practice today on most IC/ASIC projects.
The adoption trends for formal property checking (e.g., model checking) and automatic formal applications are shown in Fig. 4. We found that the adoption of formal property checking on FPGA projects is growing at an impressive 21% CAGR, and the adoption of automatic formal applications is growing at a 29% CAGR. Historically, the formal property checking process has required specialized skills and expertise. However, the recent emergence of automatic formal applications provides narrowly focused solutions and does not require specialized skills for adoption. In general, formal solutions (i.e., formal property checking combined with automatic formal applications) are one of the fastest growing segments in functional verification.
Figure 4 - FPGA project formal technology adoption trends
Fig. 5 shows the FPGA project adoption trends for various simulation-based techniques from 2012 through 2018, which include code coverage, functional coverage, assertions, and constrained-random simulation.
Figure 5 - FPGA project simulation technique trends
CONCLUSION AND DISCUSSION
In this article, we presented FPGA design and verification trends based on a recent, large industry study. FPGAs have grown in complexity equal to many of today’s IC/ASIC designs. We quantified the impact of this growing complexity in terms of verification effectiveness and effort.
Perhaps the most disturbing finding from this year’s study relates to the number of FPGA projects with non-trivial bug escapes into production. We did find an interesting correlation between the improvement of reduced functional flaws contributing to non-trivial bug escapes, as shown in Fig. 1, and the maturing of FPGA projects’ functional verification processes. The data suggest that projects that are more mature in their functional verification processes will likely experience fewer bug escapes. To test this claim, we partitioned the study participants into two groups: FPGA projects with no bug escapes and FPGA projects that experienced a bug escape. We then examined the percentage adoption of various verification techniques and the results are shown in Fig. 6. These findings are statistically significant in that the group with no bug escapes tended to have higher adoption of various verification techniques, which suggest they are more mature in their verification process. However, what we are unable to measure from our study is how effective a project was in adopting any of these processes. For example, a project that experienced a bug escape could claim that they have adopted functional coverage, yet the fidelity of their functional coverage model might be poor due to their inexperience. From our study data, we are unable to assess successful or effective adoption for any particular verification technique.
Figure 6 - FPGA simulation technique adoption versus non-trival bug escapes
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