FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension. At Baker Hughes, a top-tier oilfield service company, we primarily design small scale FPGA designs, typically less than 100 thousand gates, but our designs are growing in size and complexity. As well, they are part of more complex systems that require long lab integration times.
For these reasons, our FPGA design and verification team needed to find a new methodology that does not rely on visual checks, shortens our lab integration testing time, standardizes our testbenches, and makes our functional verification more robust.
VHDL was the language of choice for both our RTL design and testbench, but there