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by Ashley Winn, Sondrel IC Design Services
In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested. In UVM, sequences provide an ideal structure for creating test procedures at the right layer of abstraction for a particular feature. I’d like to recommend a strategy that uses default virtual sequences running on an environment- level virtual sequencer. This set up makes it easy to define and start sequences within a test, simplifies the end-of-test logic, and it allows you to move
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