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by Hari Patel & Dhaval Prajapati, eInfochips
UVM/OVM methodologies are the first choice in the semiconductor industry today for creating verification environments. Because UVM/OVM are TLM-based (Transaction Level Modeling), sequence and sequence items play vital roles and must be created in the most efficient way possible in order to reduce rework and simulation time, and to make the verification environment user friendly. This article covers how to write generic and reusable sequences so that it's easy to add a new test case or sequence. We use SRIO (Serial Rapid IO) protocol as an example.
INTRODUCTION
In UVM- and OVM-based environments, sequences are the basic building blocks directing the scenario generation process. Scenario
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