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A significant evolution is underway in SoC verification and validation.
The complexity of SoC designs has resulted in the need to perform both comprehensive verification as well as system-level validation very early in the design cycle, often before stable RTL code is available for the entire design. This same complexity has also created the need for extensive internal visibility into the design to understand subtle problems that can occur during silicon bring-up.
While the needed level of visibility can be provided with a model of the design, it requires sufficient execution speed in the modeling environment to run content that matches silicon tests to highlight issues. Hardware emulation has sufficient execution speed, full visibility
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