“...exciting new technology comes with its own set of pitfalls, many of which we may not even be aware of yet.”
Welcome to our special DAC 2016 Edition of Verification Horizons.
As I’ve said many times, DAC is undoubtedly my favorite work-related week of the year. In giving us all the opportunity to see the amazing technology that Mentor Graphics, our partners and even our competitors introduce and the chance to catch up with old friends and colleagues, it serves as an annual milestone by which we measure both the progress of our industry and the passing of time. This year, DAC happens to follow closely on the heels of a personal milestone as well. By the time you read this, my son, David, will have graduated from high school. I hope you’ll forgive a little paternal pride and allow me to tell you that he completed high school as the valedictorian of his class and will be attending Georgetown University in the fall. His mother, sister and I are, as you can imagine, extremely proud of him. I feel in some ways like we’ve reached “tape out” with this amazing young man as he goes out into the world, but of course our job is nowhere near complete. And, fortunately, we still have the summer with him.
One challenge David will have that most of us probably didn’t even consider when we graduated high school is a world with actual self-driving cars. As with anything, this exciting new technology comes with its own set of pitfalls, many of which we may not even be aware of yet. Our first article, “How Formal Techniques Can Keep Hackers from Driving You into a Ditch,” by my colleague Joe Hupcey, our Questa® Formal Product Manager, certainly lives up to its title. By walking you through a case study, Joe will first scare you and then reassure you that the proper use of formal technology can indeed protect your car, whether self-driving or automation-assisted, from being hacked, with potentially life-saving implications.
In “Simplifying HDCP Verification Using Questa® VIP (QVIP),” my colleagues from the Mentor VIP team begin with an explanation of the High-Bandwidth Digital Content Protection (HDCP) protocol, which can be used to protect critical audio and video data from third parties. Next, they lay out some of the verification challenges inherent in such a multi-step protocol, and then show how Mentor’s Display QVIP components are ideally suited for verifying this important functionality. It also serves to show some of the usability improvements we’ve made to our QVIP library.
We round out our Mentor-contributed articles in this issue with "No RTL Yet? No Problem: UVM Testing a SystemVerilog Fabric Model" by my long-time colleague Rich Edelman. This article was originally presented as a paper at DVCon-US in March, but it's so good we wanted to share it with you. Rather than your verification team needing to wait for an RTL model of the DUT, Rich shows how some of the more abstract SystemVerilog language constructs can be used to create a functional model against which you can begin building your UVM testbench and developing sequences that can be reused with the ultimate RTL model at both the block and system level.
We begin our Partners' Corner section with "Accelerating Networking Products to Market" by noted emulation expert Lauro Rizatti, a frequent contributor. In the article, Lauro walks us through the evolution of emulation for verifying a complex network SoC, such as an Ethernet switch, from in-circuit emulation (ICE), with its limited usability and complex cabling, to today's enterprise-wide reconfigurable emulation resource center using Mentor's VirtuaLAB software.