Relieving the Parameterized Coverage Headache

Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage information are well documented for designs that operate in a single configuration only. However, complications arise when parameters are introduced into the design, especially when creating customizable IP.

This article will discuss the coverage-related pitfalls and solutions when dealing with parameterized designs.