by Mark Peryer, Verification Methodologist, DVT, Mentor Graphic
A common verification requirement is to reset a design part of the way through a simulation to check that it will come out of reset correctly and that any non-volatile settings survive the process. Almost all testbenches are designed to go through some form of reset and initialization process at their beginning, but applying reset at a mid-point in the simulation can be problematic. The Accellera UVM phasing sub-committee has been trying to resolve how to handle resets for a long time and has yet to reach a conclusion.
In a UVM testbench, stimulus is generated by sequences which create and shape sequence items which are sent to a driver for conversion into pin