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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • July 2020
  • Formal Is The “New Normal” — Deploy These FV Apps In Your Next Project

Formal Is The “New Normal” — Deploy These FV Apps In Your Next Project

Verification Horizons - Tom Fitzpatrick, Editor

| Verification Horizons - July 2020 by Ajeetha Kumari, Hemamalini Sundaram, and Darshan Ballari, VerifWorks, LLC and CVC Pvt., Ltd.

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INTRODUCTION

Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in hitherto simulation-only projects. We at VerifWorks have a long history of formal deployment at many design houses and have seen the challenges engineers face while adopting the same. We have also trained hundreds of engineers to use Formal with ABV (Assertion-Based Verification) through CVC. Having such widespread experience in deploying Formal, our team has seen Formal becoming the “new normal” with many teams adopting it in their projects.

Some of the key enablers in Formal adoption are:

Availability of assertions/properties Identifying ...

Table of Contents

Verification Horizons Articles:

  • What do Grubhub®, Doordash®, and Verification Technology Have in Common?

  • Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project

  • Understanding the SVA Engine Using the Fork-Join Model

  • Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC Using Portable Stimulus

  • PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application

  • Extending SoC Design Verification Methods for RISC-V Processor DV

  • Addressing VHDL Verification Challenges with OSVVM

  • Effective Validation Method of Safety Mechanism Compliant with ISO 26262

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