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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
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      • Verification Planning and Management
      • VHDL-2008 Why It Matters

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • Home /
  • Portable Test and Stimulus

Portable Test and Stimulus

Portable Test and Stimulus

SoC verification requires more than just simulation. Multiple platforms, including emulation and FPGA prototyping, are required to verify complex designs from the block level to subsystems and full systems-on-chip. Each platform requires its own language and format for specifying tests, and these tests are often composed by different teams as well, and too much time and effort are spent recreating the same test information throughout a project. The Portable Stimulus Standard (PSS) was developed to solve this problem.

By providing a single abstract specification of verification intent, PSS allows tools, like Questa® inFact, to generate target-specific implementations of the test for the various platforms involved in verification. This frees up teams to focus on what should be tested rather than having to implement the same test multiple times. By randomizing the generation of scenarios subject to the rules and constraints defined in the abstract specification, PSS can automate the process to maximize coverage and ensure the most efficient execution of a wide range of tests on multiple platforms.

Find out more about Questa® inFact, the leading Portable Stimulus Solution.

 Portable Stimlus

Portable Stimulus Seminar

Why Portable Stimulus?

Why Portable Stimulus Session | Subject Matter Expert - Tom Fitzpatrick | Verification Academy Live Seminar

What’s all the fuss about? This introductory session sets the stage for the day by exploring the requirements to reuse stimulus and test intent throughout an SoC project which involves running different tests in different languages on different platforms at different stages of the process. It explains the value of an abstract declarative specification of verification intent and outlines the motivation and projected flow of the new Accellera Portable Stimulus Standard (PSS).

Portable Stimulus Standard Uncovered

Portable Stimulus Standard Uncovered Session | Subject Matter Expert - Tom Fitzpatrick | Verification Academy Live Seminar

This in-depth session explains the concepts in PSS and shows how you can create an abstract model of your verification intent that can be used to generate multiple scenarios implemented in UVM, C or other languages to execute on the necessary platform(s) in your verification flow.

PSS Panel Discussion

PSS Panel Discussion Session | Subject Matter Expert - Harry Foster | Verification Academy Live Seminar

Harry Foster and Tom Fitzpatrick along with guest panelists; Hugh Walsh from Marvell, Nguyen Le from Microsoft and Biju Odayammatath from Western Digital discuss the latest Portable Stimulus Standard and how you could leverage it to increase your verification productivity.

PSS Usage Examples

PSS Usage Examples Session | Subject Matter Expert - Matthew Ballance | Verification Academy Live Seminar

PSS provides features that enable test intent to be specified in a far more abstract a reusable manner than existing techniques.

In this session, two examples are used to illustrate:

- How abstract PSS test intent is easily targeted to a specific design without modifying the original test-intent description
- How PSS test intent can be enhanced to cover new requirements without modifying the original test-intent description

Wrapping Up - Where do we go from here?

Wrapping Up - Where do we go from here? Session | Subject Matter Expert - Tom Fitzpatrick | Verification Academy Live Seminar

This brief session gives an update on the projected PSS release schedule and shows how our Questa® inFact tool supports the Portable Stimulus Standard.

Portable Stimulus Basics Course

Why Portable Stimulus?

Why Portable Stimulus? Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will discuss the motivation and goals for Portable Stimulus, explore the idea of scenario-level stimulus and examine the requirements for a viable Portable Stimulus solution.

What is Portable Stimulus?

What is Portable Stimulus? Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will provide a detailed understanding of what a scenario-level test actually involves; how to think and plan at the scenario level; and how a single scenario-level specification can be used to create multiple test scenarios.

Walking Through a Portable Stimulus Example

Walking Through a Portable Stimulus Example Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

In this session, you will be walking through a simple Portable Stimulus example.

Virtual Lab

Questa® inFact Getting Started Importing a Testbench

This virtual lab tutorial includes three exercises designed to introduce you to Questa® inFact and to the process of importing existing testbench source to automate the integration of Questa® inFact into an existing verification environment. The example in this tutorial uses the Universal Verification Methodology (UVM) with SystemVerilog.

Learn more.

Related Resources

Portable Stimulus: A New Hope

DAC 2018 | Portable Stimulus: A New Hope

This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology.

Portable Stimulus from IP to SoC - Achieve More Verification

DAC 2018 | Portable Stimulus from IP to SoC - Achieve More Verification

This session will show how Mentor’s inFact portable stimulus tool is applied across the verification spectrum and the spectrum of verification engines to achieve more verification with the same resources.

Automating Reusable, Retargetable Scenario-Level Tests with Portable Stimulus

Automating Reusable, Retargetable Scenario-Level Tests with Portable Stimulus Session | Subject Matter Expert - Matthew Balance | Academy Live Web Seminar

In this session, you will learn how graph-based portable stimulus raises the abstraction level of test specification and execution, and enables tests to be retargeted across environments and execution platforms.

 

Testbench Automation: How to Create a Complex Testbench in a Couple of Hours

In 2014, the semiconductor industry passed an important milestone. For the first time, the average engineering team had more verification engineers than designers. This means that any improvement in the efficiency of verifications teams has a significant impact on overall project costs and time to market.

Verification Horizons

  • Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
  • Make Your Constraints More Dynamic with Portable Stimulus
  • Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
  • Smoothing the Path to Software-Driven Verification with Portable Stimulus
  • Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
  • Automating Tests with Portable Stimulus from IP to SoC Level
  • Bridging UVM to the Portable Stimulus Standard with Questa® inFact
  • Improving Performance and Verification of a System Through an Intelligent Testbench
  • Saving Time and Improving Quality with a Specification to Realization Flow
  • A New Stimulus Model for CPU Instruction Sets
  • Intelligent Testbench Automation with UVM and Questa®
  • Portable VHDL Testbench Automation with Intelligent Testbench Automation
  • Software-Driven Testing of AXI Bus in a Dual Core ARM® System
  • Power Up Hardware/Software Verification Productivity
  • Is Intelligent Testbench Automation For You?
  • Automated Generation of Functional Coverage Metrics for Input Stimulus
  • Targeting Internal-State Scenarios in an Uncertain World

Blog Posts

  • Applying Portable Stimulus at DAC
  • Portable Test – Portable Intent, Portable Realization, or Both?
  • Mentor Leads Portable Stimulus at DVCon US
  • Developing Tests in Reverse with Portable Stimulus
  • Verification Academy Live Seminar: Portable Stimulus
  • Test Intent, Test Realization, and Separation of Concerns
  • Portable Stimulus Specification Released for Public Review
  • Reusing Existing Descriptions with New Languages
  • DAC 54 Spotlight on "Portable Stimulus"
  • Portable Stimulus: Standard vs. Tool vs. Language
  • Portable Stimulus the Hot Topic at DVCon U.S. '17
  • DVCon U.S. 2017: Bigger and Better!
  • DVCon India 2016–Outstanding Program Awaits
  • Portable Stimulus Takes an Important Step Forward
  • Portable Stimulus Taking Center Stage at DAC
  • Standards, Partners and Industry Collaboration Update
  • Portable Stimulus Applications at DVCon 2016
  • Modeling CPU Instruction Sets with a Portable Stimulus Specification
  • Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker

Technical Papers

  • Choosing a Format for the Portable Stimulus Specification
  • Making Legacy Portable with the Portable Stimulus Specification
  • Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse
  • Boost Verification Results by Bridging the Hardware/Software Testbench Gap
  • Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
  • UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

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