Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • UVM Coding Guidelines Web Seminar - April 10th
      • Getting Started with SystemVerilog Functional Coverage Web Seminar - April 15th
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DVCon 2020 - Featured Presentations
      • DAC 2019 Session Recordings
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2020
      • Verification Horizons - December 2019
      • Verification Horizons - June 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
  • Home /
  • Topics /
  • Portable Test and Stimulus

Portable Test and Stimulus

Portable Test and Stimulus

SoC verification requires more than just simulation. Multiple platforms, including emulation and FPGA prototyping, are required to verify complex designs from the block level to subsystems and full systems-on-chip. Each platform requires its own language and format for specifying tests, and these tests are often composed by different teams as well, and too much time and effort are spent recreating the same test information throughout a project. The Portable Stimulus Standard (PSS) was developed to solve this problem.

By providing a single abstract specification of verification intent, PSS allows tools, like Questa® inFact, to generate target-specific implementations of the test for the various platforms involved in verification. This frees up teams to focus on what should be tested rather than having to implement the same test multiple times. By randomizing the generation of scenarios subject to the rules and constraints defined in the abstract specification, PSS can automate the process to maximize coverage and ensure the most efficient execution of a wide range of tests on multiple platforms.

Find out more about Questa® inFact, the leading Portable Stimulus Solution.

 Portable Stimulus

Success Story

Microsoft® boosts regression efficiency 2-3X with Questa® inFact

Shelly Henry, Quantum Computing Hardware Verification Architect at Microsoft® Corp.

Learn how Microsoft found success using Questa® inFact to overcome their functional coverage and regression challenges.

Portable Stimulus Basics Course

Why Portable Stimulus?

Why Portable Stimulus? Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will discuss the motivation and goals for Portable Stimulus, explore the idea of scenario-level stimulus and examine the requirements for a viable Portable Stimulus solution.

Concepts & Language Introduction

Concepts & Language Introduction Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will provide a detailed understanding of what a scenario-level test actually involves; how to think and plan at the scenario level; and how to use the constructs in the Portable Test and Stimulus Standard to describe a scenario-level test.

Test Realization

Test Realization Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will walk you through the steps of how to define target-platform implementations for the elements of a Portable Stimulus model and how a Portable Stimulus tool can assemble these elements into a functional test on the target platform.

Importing UVM into Portable Stimulus

Importing UVM into Portable Stimulus Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will show how to take advantage of Portable Stimulus automation to augment your existing UVM environment. You will learn how a Portable Stimulus tool like Questa® inFact can import transactions and functional coverage to generate more efficient scenario-level tests guaranteed to reach your coverage goals and how to easily integrate this automation into your regression environment.

Featured Learning Path

Questa Simulation Coverage Acceleration Apps with inFact Learning Path

In this learning path you will learn to use Questa inFact PSS to generate portable stimulus and achieve coverage faster than other stimulus generation methods.

Exercises include:

  • Chapter 1: Stimulus Optimization with inFact
  • Chapter 2: Regression Optimization with inFact
  • Chapter 3: Coverage Goal Optimization with inFact
  • Chapter 4: Scenario Generation Optimization with inFact and PSS

FREE 30 day trial subscription.

Learn more.

Questa® inFact Related Resources

  • Articles
  • Blog Posts
  • White Papers
  • On-Demand
  • News
  • Seminar
  • Accellera
  • Product Information

Featured Portable Stimulus & Test Verification Horizons Articles

  • Exercising State Machines with Command Sequences
  • Designing A Portable Stimulus Reuse Strategy
  • Creating Tests the PSS Way in SystemVerilog
  • Auto-Generating Implementation-Level Sequences for PSS
  • Selecting a Portable Stimulus Application Focal Point
  • Building a Better Virtual Sequence with Portable Stimulus
  • Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
  • Make Your Constraints More Dynamic with Portable Stimulus
  • Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
  • Smoothing the Path to Software-Driven Verification with Portable Stimulus
  • Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
  • Automating Tests with Portable Stimulus from IP to SoC Level
  • Bridging UVM to the Portable Stimulus Standard with Questa® inFact
  • Improving Performance and Verification of a System Through an Intelligent Testbench
  • Saving Time and Improving Quality with a Specification to Realization Flow
  • A New Stimulus Model for CPU Instruction Sets
  • Intelligent Testbench Automation with UVM and Questa®
  • Portable VHDL Testbench Automation with Intelligent Testbench Automation
  • Software-Driven Testing of AXI Bus in a Dual Core ARM® System
  • Power Up Hardware/Software Verification Productivity
  • Is Intelligent Testbench Automation For You?
  • Automated Generation of Functional Coverage Metrics for Input Stimulus
  • Targeting Internal-State Scenarios in an Uncertain World

Featured Portable Stimulus & Test Blog Posts

  • Portable Stimulus: Are you Ready for a Verification Revolution
  • Portable Stimulus and the Prius Model of New Technology Adoption
  • Taking the First Step in Portable Stimulus Adoption
  • Cats != Coverage
  • It Don’t Mean a Thing … Without Methodology
  • Better Virtual Sequences with Portable Stimulus
  • Prospecting for Reusable Assets with Portable Stimulus
  • Applying Portable Stimulus at DAC
  • Portable Test – Portable Intent, Portable Realization, or Both?
  • Developing Tests in Reverse with Portable Stimulus
  • Verification Academy Live Seminar: Portable Stimulus
  • Test Intent, Test Realization, and Separation of Concerns
  • Portable Stimulus Specification Released for Public Review
  • Reusing Existing Descriptions with New Languages
  • DAC 54 Spotlight on "Portable Stimulus"
  • Portable Stimulus: Standard vs. Tool vs. Language
  • Portable Stimulus the Hot Topic at DVCon U.S. '17
  • DVCon U.S. 2017: Bigger and Better!
  • DVCon India 2016–Outstanding Program Awaits
  • Portable Stimulus Takes an Important Step Forward
  • Portable Stimulus Taking Center Stage at DAC
  • Standards, Partners and Industry Collaboration Update
  • Portable Stimulus Applications at DVCon 2016
  • Modeling CPU Instruction Sets with a Portable Stimulus Specification
  • Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker

Featured Portable Stimulus & Test White Papers

  • Results Checking Strategies with Portable Stimulus
  • Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
  • Managing and Automating HW/SW Tests from IP to SoC
  • Boost Verification Results by Bridging the Hardware/Software Testbench Gap
  • Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
  • UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Featured Portable Stimulus & Test On-Demand Technical Sessions

  • How to Close Coverage 10X Faster A Case Study Using Questa inFact
  • Portable Stimulus: A New Hope
  • Portable Stimulus from IP to SoC - Achieve More Verification
  • Automating Reusable Retargetable Scenario-level Tests with Portable Stimulus
  • Testbench Automation: How to Create a Complex Testbench in a Couple of Hours
  • Automating Scenario-Level UVM Tests with Portable Stimulus
  • New School Stimulus Generation Techniques

Featured Portable Stimulus & Test News & Press

  • Make It Easier to Exercise State Machines with SystemVerilog
  • Portable Stimulus And Digital Twins
  • Mentor boosts 64-bit Arm-based server platform by enabling Arm architecture support for Questa simulation tools
  • Find the Fastest Route to Portable Stimulus Tests with SystemVerilog
  • The Growing Impact Of Portable Stimulus
  • PSS and Reuse: Great Solution But Not Hands-Free
  • The Nuts and Bolts of Verification - Recasting SystemVerilog for Portable Stimulus
  • How to Create and Run Reusable Register-Test Models
  • Verification’s Next Steps - Portable Stimulus and You
  • Retargeting Existing Tests in an Integrated SoC Verification Flow
  • Create more flexible virtual sequences with Portable Stimulus
  • Accellera Approves New Portable Test and Stimulus Standard
  • Accellera Approves New Portable Test and Stimulus Standard - Quote Sheet
  • Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification
  • Portable Stimulus in High-Level Synthesis Flow
  • An Incremental Approach To Reusing Automated Tests From IPs To SoCs
  • Raising SoC Development Productivity With Portable Stimulus
  • Portable Stimulus Intent - Accellera's New Standard Goes to Early Adopters
  • Accellera Portable Stimulus Early Adopter Specification Now Available for Public Review
  • Mentor Verification Is First to Deliver Portable Stimulus Technology Across the Full Enterprise Verification Platform
  • Automating test from IP to SoC levels with portable stimulus
  • Portable Stimulus: The Making of a Standard
  • Developing the Portable Stimulus Standard
  • Early access view of portable-stimulus standard released
  • Portable Stimulus - Practice Guide
  • Verification Unification: Part 1 | Part 2 | Part 3
  • Tools suppliers back version 1.0 of portable-stimulus standard
  • Cadence, Mentor Graphics and Breker Announce Collaborative Technology Contribution to Accellera Portable Stimulus Working Group

Featured Portable Stimulus & Test Seminar

  • Why Portable Stimulus?
  • Portable Stimulus Standard Uncovered
  • PSS Panel Discussion
  • PSS Usage Examples
  • Wrapping Up - Where do we go from here?

Accellera Standards

  • Portable Stimulus Downloads - Manual, Release, Notes, Errata
  • Portable Stimulus Public Review Forum
  • Portable Test and Stimulus: The Next Level of Verification Productivity is Here - Technical Tutorial
  • Creating Portable Stimulus Models with the Upcoming Accellera Standard
  • Portable Stimulus Updates - DVCon Europe 2015 - Video Updates
  • Portable Stimulus Specification - Early Adopter Release
  • Portable Stimulus Specification Working Group

Portable Stimulus Testbench Automation Solution

Questa® inFact is the industry’s most advanced Portable Stimulus testbench automation solution. It targets as much functionality as traditional constrained random testing, achieves coverage goals 10X to 100X faster, and scales across block, subsystem, and SoC level.
This enables engineering teams to complete their functional verification process in less time, and/or to expand their coverage goals, testing functionality that previously fell below the cut line.

Questa inFact also generates tests that an engineer might not envision, reaching difficult corner cases that alternative testing techniques typically miss. Using Questa inFact technology ensures high quality products.

Learn more | Datasheet

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock