Safety Analysis for Automotive Chips Based on ISO 26262
In this webinar, we will be focusing on the usage of SafetyScope at various stages of a safety design cycle: architectural phase, RTL phase and post-synthesis phase. We will also demo showing initial FIT calculations as well as the ISO 26262 metrics, what if analysis and exploration to reach ASIL B safety.
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Session Registration
Session Registration
Date and Time
- Wednesday, March 12th
- 8:00 AM US/Pacific
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Session Resources
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Session Overview
SafetyScope for safety analysis plays a key role in the overall safe-IC development process.
Calculating FIT rate, Safety exploration, generating optimized fault lists and final metric validation to name a few.
In this webinar, we will be focusing on the usage of SafetyScope™ at various stages of a safety design cycle: architectural phase, RTL phase and post-synthesis phase.
We will show a demo showing initial FIT calculations as well as the ISO 26262 metrics, what if analysis and exploration to reach ASIL B safety.
We will show how to generate an optimized fault list and show how statistical random sampling can generate a fault list to further optimize your fault campaigns with confidence in the metric results.
We will also talk about the input and output logs and metrics to watch out for in each step.
What You Will Learn
- Safety analysis steps to be done at various stages of chip development.
- FIT rate calculations and additional metric calculations using SafetyScope.
- Safety exploration phase to achieve a desired DC/ASIL target.
- Generate an optimized fault list.
Who Should Attend
- Design and Verification Engineers who are interested in learning more about functional safety.
Products Covered
- SafetyScope