New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming FPU Webinar

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Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

A Path to Develop Safe ICs - Part 2

In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.

Stephanie Dournelle, Paul Williams - Siemens EDA

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