Streamlining FPU Verification with an Alternative to C-reference Model Approaches
In this session, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process).In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
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Session Registration
Session Registration
Date and Time
- Wednesday, January 22nd
- 8:00 AM US/Pacific
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Session Overview
Please join us to explore the latest methods for streamlining the verification of Floating-Point Units (FPUs), which are key components in AI applications and beyond. Ensuring that FPUs comply with the IEEE 754 standard and identifying corner-case issues using traditional simulation methods is challenging. This webinar will introduce you to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process).
What You Will Learn
- Why FPUs are critical for AI applications given their essential role in enhancing the performance and precision of AI algorithms.
- The challenges posed by floating-point unit verification, including the various complexities and special cases that make FPU verification difficult.
- Why existing FPU C++ reference model verification approaches are difficult to implement given their limitations and maintenance challenges
- The property checking approach in verifying FPU implementations -- how it can effectively and efficiently verify FPU designs; ensuring their accuracy and reliability.
Who Should Attend
- RTL Design Engineers
- Design Integrators
- Design Verification Engineers
Products Covered
- Questa Verify Property
- Questa Equivalent RTL
- Questa FPU