Explore How to Protect Against Data Corruption with Formal Security Verification
In this session, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
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Session Registration
Session Registration
Date and Time
- Wednesday, February 5th
- 8:00 AM US/Pacific
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Session Overview
Key challenges in security verification include ensuring data confidentiality, integrity, and inversion, mitigating the exploitation of sneak paths, addressing inefficient verification flows, and managing added complexity. Explore how formal technology uniquely guarantees the security requirements of datapaths. Our methodology introduces high automation to expedite the security verification process, demonstrating its applicability and debugging capabilities in a RISC-V implementation.
We will present key findings, providing detailed explanations and runtime insights, highlighting the effectiveness of the approach in enhancing security verification. Join us to learn how to tackle these challenges and improve the robustness of your hardware security verification.
What You Will Learn
Importance of Hardware Security:
- Understand why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems.
- Learn about the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
Security Verification Challenges:
- Explore the multifaceted challenges in security verification, such as ensuring data confidentiality, integrity, and inversion.
- Delve into specific issues like the exploitation of sneak paths, inefficiencies in verification flows, and the added complexity in modern hardware designs.
Formal Methodology Overview
- Gain insights into how formal technology stands out as the most reliable method for guaranteeing security requirements in hardware datapaths.
- Discover how our methodology leverages high automation to expedite the security verification process, with a focus on its applicability and debugging capabilities.
Who Should Attend
- RTL Design Engineers
- Design Integrators
- Design Verification Engineers
Products Covered
- Questa Inspect
- Questa Verify Secure
- Questa Verify Property
- Questa Verify Trust