Questa CDC-FX: Metastability Effects Delay Modeling

Introduction

Digital simulation relies on abstract behavioral models of circuits to predict how hardware designs behave. A fundamental rule that simulation relies on is that the design does not violate the setup and hold constraints specified for clocked elements. This is why extensive timing analysis complements digital simulation — to verify that, given a particular clock frequency, the setup and hold constraints are adhered to, and therefore, the simulation results are valid.

However, with the ubiquity of asynchronous clocks in today's chips, designers can't help but violate this basic design rule. Any time data is transferred between asynchronous clock domains, the signals (referred to as clock-domain-crossing or CDC signals) carrying this data will, at some point in time, violate the setup and hold constraints specified for the receiving registers. When this happens, these registers become metastable—they will not settle to either a logical 1 or 0 within the delay specified for normal operation.

To prevent metastable signals from propagating through the design, designers use specific circuits, called synchronizers, to connect asynchronous clock domains. While virtually eliminating the possibility that metastable values will contaminate the design, synchronizers do introduce non-deterministic delays.

Regular RTL simulation is a deterministic process and does not model the non-determinism of metastability, so designers require ways to verify that the design’s functionality is not impacted by the non-deterministic delays introduced by metastability.

Accurately modeling non-deterministic metastability delays is specifically important for designs that exhibit sequential reconvergence; in …