Clock-Domain Crossing Challenges in Latch-Based Designs

Clock-domain crossing (CDC) analysis for registers and memories are well understood problems ^[1] and there are many software tools to analyze the CDC issues associated with them. However, presence of latches in the designs can complicate CDC analysis as some of the latches may act as pass through combinatorial paths through which the input signal can continuously affect the output of the latch. Still, latches are a necessary part of high-performance designs due to their advantages in time borrowing and ability to tolerate on chip variance.

This paper describes the challenges in CDC analysis for latch-based designs and a systematic approach to handle latches that are not enabled by clock signals. It also presents the results and insights of latch-based crossings for several industrial scale designs.

Why Designs Have Latches:

Latches are bistable storage elements that are transparent when the enable signal is active ^[5]. Latches and registers are both sequential elements, as their outputs depend on their previous states. However, latches are different from flip flops as they are level sensitive instead of being edge triggered as in the case of registers.

Latches are more difficult to handle in static timing analysis ^[2] and testability ^[3] due to time borrowing and transparent operation in the enabled phase. But they are still used in high performance designs due to their faster timing, smaller area and lower power benefits. When latches are involved in CDC paths, it becomes even harder to understand the paths going through such latches and ensure proper functioning. Synthesis tools generally do not
create latches because of the aforementioned difficulties. Appearance of latches in synthesized netlists often indicates incorrect RTL coding, such as an incomplete assignment [6]. When performing clock domain analysis, special attention must be paid to these latches to avoid metastability ^{[3] [4]}.

Clock-Domain Crossings Involving Latches

The latch enable is typically a clock, so that timing the paths involving the latch is easier. But it is not always the case, since the enable of the latch can simply be a sampling signal composed of other non-clock signals. If CDC analysis will treat the enables of latches as clocks, it could result in spurious clock signals and false CDC paths. For this reason, we cannot always infer that the signal connected to the enable pin of the latch is a clock. Such latches are generally called unclocked latches.

This is different from the derived clocks for registers, since the clock distribution network has to be glitch free and is designed for low skew, low slew, and minimal jitter. So, it is quite atypical to see arbitrary logic in the clocking network. Typical logic encountered in clock distribution networks are dividers, multipliers (PLLs), buffers, clock muxes and clock gating cells. For example, combining two clocks derived from the same clock can result in unpredictable clocking waveforms, particularly when circuit delays are taken into account. Special structures are necessary for multiplexing different clocks ^[7].

The clock waveform must also exhibit low slew, i.e.: fast rise and fall times, to increase the usable clock period for propagation delays of other signals. But for latches, it is not uncommon to see more complex logic in its enable as jitters or skews are not an issue when the latch is used as an unclocked latch and is not connected directly to another such latch. In fact, most CDC tools check for improper logic gates in the clock tree logic. Those checks should not be applied on control signals that control the latch enables.