New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific


  1. Introduction

    Modern System-on-a-Chip (SoC) designs incorporate hundreds of Semiconductor Intellectual Property (SIP) blocks, resulting in complex reset architectures, with many asynchronous reset domains [1]. The complex reset architectures enables transmission of data across sequential elements reset by different asynchronous reset domains thereby causing reset domain crossings (RDC) paths [1,2]. For RDC paths, an asynchronous reset at the source register may cause a destination register to sample an asynchronous event and become metastable. This metastability will cause unpredictable values to be propagated to down-stream logic and prevents a design to reset to a known good state which makes device power-up unreliable. In the worst case, reset issues may cause a device to consume too much power during assertion of reset, causing the device to be permanently damaged.

    This paper presents a specification-driven methodology for the design and verification of RDC paths in real-world SoC designs. This methodology is a systematic and repeatable solution that includes:

    • Step 1: RDC design requirements specification and verification plan
    • Step 2: RDC design and verification
    • Step 3: RDC results progress tracking and completion metrics

    This RDC methodology is supported by an integrated requirements management capability to enable requirements traceability. We describe how the incorporation of RDC design requirements improves the design and verification process and creates a systematic approach for designing and verifying the reset architecture. Finally, the incorporation of coverage allows the correlation between the design requirements and verification efforts and enables closure for the verification process.

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