Released on May 18th, 2021.
As the industry increases investments in automotive and safety-critical design, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. An increasing number of companies deploy CDC verification at both the RTL and the gate-level. To identify potential glitches on CDC paths at the gate-level, we use Signoff CDC, a tool that utilizes structural CDC analysis, expression analysis, and formal methods to prune and prove real glitches in the design.
This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs.
What You Will Learn:
- Why you need to be running gate-level CDC verification
- How to identify and fix the “three witches” that cause glitches and break CDC paths
- How to add netlist CDC to your CDC flow