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Setting Up the Register Layer

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Setting Up the Register Layer Session | Subject Matter Expert - Tom Fitzpatrick | Advanced UVM Course

Session Details

This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT. It shows how to set up the address map of registers and how to convert a register-level transaction into a bus-level transaction. It also shows how the Register Assistant tool in Certe Testbench Studio can be used to create correct-by-construction register models from a specification.