Released on October 15th, 2020
Whether you are designing an ASIC or FPGA, it is often beneficial to use as many non-resettable registers or flip flops as possible: such elements are often significantly smaller than their fully-resettable counterparts, consume less power, and have a higher operational frequency. But how can you conclusively determine the maximum number of these elements that you can safely use without risking the creation of harmful ‘X’ signal corruption that could lead to unpredictable behavior in silicon?
Fortunately, “there’s an app for that”: Questa X-Check is an automated application that uses formal algorithms under-the-hood to exhaustively root out ‘X’ issues; but you don’t need to know Formal to use it. In this webinar we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process. Results from real world case studies of this flow will be included.
What You Will Learn:
- A brief review of ‘X’ initialization, propagation, and corruption issues
- A Formal-Based ‘X’ verification flow
- A real world case study employing this exact methodology
