Release date: November 9th, 2023.
Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.
In this webinar, we will show how you can employ this capability from the software world to optimize Verilog, SystemVerilog, or VHDL code for RTL simulations.
What You Will Learn
- What is profiling, and how it applies to RTL design
- How to employ a profiler to identify and remove wall-clock run time and excessive memory usage bottlenecks in your Verilog, SystemVerilog, or VHDL DUT code
- Coding style tips to avoid creating bottlenecks in the first place
- Prerequisite: familiarity with writing Verilog, SystemVerilog, or VHDL
Who Should Attend
- RTL design and verification engineers
What/Which Products are Covered
- Questa Prime RTL simulation
- Questa Visualizer