Released on February 25th, 2022.
Designers of FPGA-based designs face any number of challenges including ensuring the behavior and functionality of the design, circumventing the increasing supply chain threat, or extending the life of legacy designs powered by old or obsolete FPGAs.
When it comes to ensuring design functionality, gate-level simulation takes too long and verifying that the gate-level netlist matches the corresponding RTL is extremely tough to do. The OneSpin Formal Equivalence Checking solution alleviates these issues to produce the highest quality of results while reducing time-to-market, cost, and development schedules. EC-FPGA ensures that bugs introduced by synthesis are caught. Exhaustive verification is done to ensure functional equivalence of RTL code to synthesized netlist and final place-and-routed FPGAs.
This technology can also be used to solve 2 other major challenges facing FPGA-based designs: 1) The recent supply chain issues that are making certain FPGAs scarce forcing development teams to find alternatives and 2) How to extend the life of a legacy design that is still viable but is based on old or obsolete FPGA technology. Redesigning the device for new or different FPGAs can take months if not years. Re-synthesizing the RTL to meet the desired new technology may also not be feasible. The latest RTL synthesis tools might not produce equivalent results because the tools’ interpretation of the RTL will most likely not be the same as the original synthesis tools’ that was used.
Both obstacles can be sidestepped by retargeting designs to new, cheaper, and or available FPGA devices. For legacy designs, retargeting also ensures that designs are brought up to the latest safety and security standard while reducing power consumption. This unique retargeting technology based on OneSpin EC-FPGA is the perfect solution for design teams to pivot to available FPGAs as well as ensure that legacy designs can live on. As a result, design teams on both spectrums can reduce costs and save months of redesign time leading to faster time-to-market.
In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs. This webinar will outline the verification solutions and retargeting solutions to address these challenges. A workflow and methodology will be provided for each scenario along with real world case studies.
What You Will Learn:
- The challenges facing FPGA-based designers
- Mitigating FPGA supply chain shortages and legacy design dilemma
- The verification strategies to ensure FPGA-based designs have zero bug escapes
Who Should Attend:
- Design & Verification Engineers & Managers using FPGAs
- Program Managers & Systems Developers