Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
Debug is one of the most time-consuming tasks verification engineers face in the design and verification of FPGAs, IPs and SoCs. Visualizer provides an advanced debug environment that includes many tools to help with both post-simulation and live-simulation debug.
This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.
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