Released on July 14th, 2020
Chris Spear, Principle Instructor, presents a detailed description of structures and packages in the SystemVerilog language. You can model your hardware registers down to the bit level, or build complex data types that contain a mix of different elements such as 4-state logic, 2-state integers, real numbers, and enumerated types. In addition, you will be shown how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused. We will also be discussing problems and best practices with packages.
What You Will Learn:
- How to build simple structures for modeling hardware
- How to read and write structures, both individual values, and various subsets, plus assignment between structures
- How to declare an array inside a structure, an array of structures, and building scoreboard blocks
- How to pack the elements of a structure so it more closely models real hardware
- Passing a structure through a module port
- The $unit global declaration space and why it should be avoided
- How to group declarations into SystemVerilog packages
- Where to import packages into your modules
- How to organize classes and files when using packages/li>
- How to solve name conflicts with multiple packages
- How to create layers of packages with import and export statements
- How to solve a common issue with chaining packages
